fix(riscv): enforce execution, CSR, and SMIR constraints

[19h]

Summary

This independently reimplements, validates, and consolidates the RISC-V fixes proposed in #218, #220, #222, #224, #226, #228, #230, #233, #235, #237, #239, #241, and #244.

No contributor commits were cherry-picked or merged, and no contributor code was copied into this branch. The implementation was derived from the issue reproductions, the repository's current execution paths, and the RISC-V unprivileged/privileged architecture requirements. Carlos is credited as co-author on every rollup commit.

Fixes #217
Fixes #219
Fixes #221
Fixes #223
Fixes #225
Fixes #227
Fixes #229
Fixes #232
Fixes #234
Fixes #236
Fixes #238
Fixes #240
Fixes #243

Changes

• enforce IALIGN=32 for SMIR JAL, branch, and dynamic JALR when C is disabled; reject reserved JALR funct3 values
• gate FENCE.I, CSR, floating-point CSR, and vector CSR lifting on the required ISA extensions
• preserve loads to x0 as observable, faulting memory operations in optimized and native execution
• apply architectural WARL/projection rules to mepc, misa, and mtvec
• reject unavailable CSR families, including RV32-only high counters on RV64 and extension-owned FP/vector/JVT CSRs
• count only normally completed instructions in instret; ECALL, EBREAK, and synchronous traps do not retire
• require D for compressed double-precision memory operations while preserving Zcmp/Zcmt overlay decoding
• fail closed before native execution for predecoded illegal compressed instructions
• validate failed SC.W/SC.D store ranges on direct and native paths, clear reservations at the correct point, and use a non-mutating backend probe so permission checks do not cause MMIO reads
• correct Zcmp rlist=5 to {ra,s0} in compressed decode sizing, direct execution, disassembly, and SMIR/JIT while preserving the three-register rlist=6 behavior
• split RISC-V control flow, CSR handling, and execution accounting out of oversized source modules

Validation

Each regression probe reproduced the reported defect against the pre-fix baseline before passing with the independent implementation.

• fresh GitHub matrix on the final head: all 24 checks passed, including four host core-test lanes, the full cross-build matrix, formatting/Clippy, and both microkernel runs
• exhaustive final-tree library gate: 8,267 passed, 0 failed, 0 ignored
• direct plus production O0/O2 JIT regression coverage for control flow, load-to-x0, CSR traps, retirement, illegal native admission, SC.W/SC.D faults, and Zcmp register-list semantics
• RISC-V module slice: 155 passed
• exhaustive SMIR lift/oracle target: 13 passed
• native x86-64 RISC-V SMIR/JIT target: 36 passed
• live QEMU RISC-V scalar differential target: 30 passed, 0 skipped
• independent Zcmp oracle check: LLVM decodes 0xb852 as cm.push {ra, s0}, -16 and 0xb856 as cm.push {ra, s0}, -32, matching the current RISC-V Zcmp register-list and stack-adjustment tables
• cargo fmt --all --check
• cargo clippy --all-targets --features x86_64-suite
• cargo build --all-targets --no-default-features --features x86_64-suite,smir-jit

Integration note

This PR is intentionally stacked on #203 so it inherits the already reviewed and green CI/cross/microkernel repairs there. After #203 merges, this PR should be retargeted to master.

#203 independently covers the earlier contributor series #197, #198, #199, #200, #201, #202, #206, #208, #210, #212, #214, and #216. No commits from those PRs are included here either.

@carlosqwqqwq, thank you for reporting these architecture gaps. Please review this consolidation, especially the conservative no-C JALR fallback, extension/CSR profile combinations, compressed overlay handling, native illegal-instruction frontier, failed-SC exception ordering/probe behavior, and the Zcmp rlist=5/rlist=6 boundary and RV32/RV64 stack adjustments.

[19h]

@carlosqwqqwq — the independent consolidation is complete at 3f57107d and all 24 GitHub checks are green.

#231 now covers #218, #220, #222, #224, #226, #228, #230, #233, #235, #237, #239, #241, and #244, with the corresponding issues linked for closure on merge. No commits or code were taken from those PRs; the fixes were independently reproduced, reimplemented, and validated, and every rollup commit credits you through the GitHub co-author trailer.

The latest addition corrects Zcmp rlist=5 across decode sizing, direct execution, disassembly, and SMIR/JIT, with rlist=6 boundary coverage and independent specification/LLVM oracle checks. Please review the consolidated implementation, especially the architectural fallback frontiers, extension/CSR gates, failed-SC ordering, and Zcmp RV32/RV64 stack-adjustment behavior.

[19h]

The next independently implemented validation batch is now consolidated in #255, covering #245–#249 and superseding #250–#254. This keeps the follow-up chain from #203/#231 explicit and retains Carlos as co-author.

[19h]

Follow-up validation and independently reimplemented RISC-V fixes now continue in #296. It consolidates the newly reported vector-memory, operand-validation, SRET, and WFI gaps, carries contributor credit, and is ready for review.