Skip to content

Actions: HexRaysSA/rax

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
2,500+ workflow runs
2,500+ workflow runs

Filter by Workflow

⌥ + click/return to exclude

Filter by Event

⌥ + click/return to exclude

Filter by Status

⌥ + click/return to exclude

Filter by Branch

⌥ + click/return to exclude

Filter by Actor

⌥ + click/return to exclude
feat(x86_64): natively lower legacy ptest CI #1180: Commit 7b07d83 pushed by 19h
25m 25s master
master
25m 25s
feat(x86_64): natively lower legacy ptest Cross-build #1240: Commit 7b07d83 pushed by 19h
3m 12s master
master
3m 12s
feat(x86_64): natively lower legacy ptest Microkernel #5682: Commit 7b07d83 pushed by 19h
3m 6s master
master
3m 6s
feat(x86_64): natively lower legacy pclmulqdq Microkernel #5681: Commit 9e77c54 pushed by 19h
3m 7s master
master
3m 7s
feat(x86_64): natively lower legacy pclmulqdq CI #1179: Commit 9e77c54 pushed by 19h
20m 51s master
master
20m 51s
feat(x86_64): natively lower legacy pclmulqdq Cross-build #1239: Commit 9e77c54 pushed by 19h
5m 8s master
master
5m 8s
fix(riscv): require aligned register groups for vsaddu/vsadd/vssubu/vssub CI #1178: Pull request #284 synchronize by carlosqwqqwq
35m 24s carlosqwqqwq:fix-riscv-vsaddu-family-align
carlosqwqqwq:fix-riscv-vsaddu-family-align
35m 24s
fix(riscv): require aligned register groups for vsaddu/vsadd/vssubu/vssub Microkernel #5680: Pull request #284 synchronize by carlosqwqqwq
3m 19s carlosqwqqwq:fix-riscv-vsaddu-family-align
carlosqwqqwq:fix-riscv-vsaddu-family-align
3m 19s
fix(riscv): require aligned register groups for vsaddu/vsadd/vssubu/vssub Cross-build #1238: Pull request #284 synchronize by carlosqwqqwq
23m 31s carlosqwqqwq:fix-riscv-vsaddu-family-align
carlosqwqqwq:fix-riscv-vsaddu-family-align
23m 31s
feat(x86_64): natively lower legacy insertps Cross-build #1237: Commit d84e65f pushed by 19h
12m 5s master
master
12m 5s
feat(x86_64): natively lower legacy insertps CI #1177: Commit d84e65f pushed by 19h
40m 50s master
master
40m 50s
feat(x86_64): natively lower legacy insertps Microkernel #5679: Commit d84e65f pushed by 19h
3m 13s master
master
3m 13s
feat(x86_64): natively lower legacy FP dot product Microkernel #5678: Commit f5ba8dd pushed by 19h
2m 24s master
master
2m 24s
feat(x86_64): natively lower legacy FP dot product CI #1176: Commit f5ba8dd pushed by 19h
47m 24s master
master
47m 24s
feat(x86_64): natively lower legacy FP dot product Cross-build #1236: Commit f5ba8dd pushed by 19h
43m 5s master
master
43m 5s
fix(riscv): reject masked vector instructions writing v0 Cross-build #1235: Pull request #272 synchronize by carlosqwqqwq
48m 33s carlosqwqqwq:fix-riscv-masked-vd-v0
carlosqwqqwq:fix-riscv-masked-vd-v0
48m 33s
fix(riscv): reject masked vector instructions writing v0 Microkernel #5677: Pull request #272 synchronize by carlosqwqqwq
3m 15s carlosqwqqwq:fix-riscv-masked-vd-v0
carlosqwqqwq:fix-riscv-masked-vd-v0
3m 15s
fix(riscv): reject masked vector instructions writing v0 CI #1175: Pull request #272 synchronize by carlosqwqqwq
1h 6m 55s carlosqwqqwq:fix-riscv-masked-vd-v0
carlosqwqqwq:fix-riscv-masked-vd-v0
1h 6m 55s
fix(riscv): require aligned register groups for vsaddu/vsadd/vssubu/vssub Microkernel #5676: Pull request #284 synchronize by carlosqwqqwq
3m 31s carlosqwqqwq:fix-riscv-vsaddu-family-align
carlosqwqqwq:fix-riscv-vsaddu-family-align
3m 31s
fix(riscv): require aligned register groups for vsaddu/vsadd/vssubu/vssub CI #1174: Pull request #284 synchronize by carlosqwqqwq
50m 58s carlosqwqqwq:fix-riscv-vsaddu-family-align
carlosqwqqwq:fix-riscv-vsaddu-family-align
50m 58s
fix(riscv): require aligned register groups for vsaddu/vsadd/vssubu/vssub Cross-build #1234: Pull request #284 synchronize by carlosqwqqwq
6m 51s carlosqwqqwq:fix-riscv-vsaddu-family-align
carlosqwqqwq:fix-riscv-vsaddu-family-align
6m 51s
fix(riscv): require aligned register groups for vssrl/vssra Cross-build #1233: Pull request #285 synchronize by carlosqwqqwq
36m 17s carlosqwqqwq:fix-riscv-vssrl-vssra-align
carlosqwqqwq:fix-riscv-vssrl-vssra-align
36m 17s
fix(riscv): require aligned register groups for vssrl/vssra CI #1173: Pull request #285 synchronize by carlosqwqqwq
57m 49s carlosqwqqwq:fix-riscv-vssrl-vssra-align
carlosqwqqwq:fix-riscv-vssrl-vssra-align
57m 49s
fix(riscv): require aligned register groups for vssrl/vssra Microkernel #5675: Pull request #285 synchronize by carlosqwqqwq
3m 2s carlosqwqqwq:fix-riscv-vssrl-vssra-align
carlosqwqqwq:fix-riscv-vssrl-vssra-align
3m 2s
fix(riscv): require aligned register groups for vslide1down/vfslide1down Microkernel #5674: Pull request #291 synchronize by carlosqwqqwq
3m 7s carlosqwqqwq:fix-riscv-vslide1down-align
carlosqwqqwq:fix-riscv-vslide1down-align
3m 7s