fix(riscv): require aligned register groups for vssrl/vssra

[carlosqwqqwq]

Closes #280

Summary

The scaling shift instructions vssrl and vssra name vector register groups in vd, vs2 and (for the .vv form) vs1, and the RISC-V V extension requires each group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected Vssrl | Vssra branch executed the shift without any register-group alignment check, so reserved encodings such as vssrl.vv v1, v2, v2 with e32/m2 (vd=v1 misaligned) were executed. QEMU raises SIGILL for these encodings via opivv_check/opivx_check.

The fix rejects any .vv form with a misaligned vd, vs1 or vs2, and any .vx/.vi form with a misaligned vd or vs2, computing EMUL from vtype.

Validation

• cargo test --lib: the targeted scaling-shift alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated the scaling-shift alignment gap, then reimplemented it through the shared RVV validator with expanded tests in #296. The rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296.