fix(riscv): require aligned register groups for vslide1down/vfslide1down

[carlosqwqqwq]

Closes #286

Summary

The downward-slide-by-one instructions vslide1down and vfslide1down name vector register groups in vd and vs2, and the RISC-V V extension requires each group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected Vslide1down | Vfslide1down branch executed the slide without any register-group alignment check, so reserved encodings such as vslide1down.vx v0, v1, x5 with e32/m2 (vs2=v1 misaligned) were executed. QEMU raises SIGILL for these encodings via slidedown_check -> vext_check_slide(..., is_over=false).

The fix rejects a misaligned vd or vs2, computing EMUL from vtype, while keeping vd == vs2 legal (as the spec permits for the downward direction).

Validation

• cargo test --lib: the targeted vslide1down alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated the slide-down alignment gap, then reimplemented it through the shared RVV validator with direct and SMIR/JIT coverage in #296. The rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296.