fix(riscv): reject compressed double-precision memory ops without D - #237
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carlosqwqqwq wants to merge 2 commits into
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fix(riscv): reject compressed double-precision memory ops without D#237carlosqwqqwq wants to merge 2 commits into
carlosqwqqwq wants to merge 2 commits into
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cpu.rs exceeded the AGENTS.md hard split triggers (2000 lines / 150 kB). Move the vector (RVV) element access and data-path execution group, including set_vtype, into cpu/vector.rs with no behavior change.
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Thank you for reporting and proposing this fix. I independently reimplemented and validated D-extension gating for all four compressed double-precision memory forms, including Zcmp/Zcmt overlay controls in the consolidation PR #231; no commits or code from this branch were taken. The rollup carries @carlosqwqqwq as co-author on its commits and includes direct and native regression coverage. I’m closing this PR as superseded by #231—please review the consolidated implementation there. |
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fix(riscv): reject compressed double-precision memory ops without D
Closes #236
Summary
The C extension's double-precision floating-point load/store encodings (C.FLD, C.FSD, C.FLDSP, C.FSDSP) require the D extension. Under an RV64IMAC profile these halfwords are reserved and must decode as illegal. RAX's direct RVC decoder reaches the floating-point operation without checking
isa.d, making profile-gated code executable when the guest does not have D.The fix adds the same D check to all four decoder arms in the compressed decoder.
Validation
c_float_mem_rejected_without_dfails on the base checkout and passes with the fix.cargo test --lib: full library test suite passes with no regressions.No new upstream test files are added; this is a source-only change.