Skip to content

fix(riscv): reject compressed double-precision memory ops without D #237

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
carlosqwqqwq wants to merge 2 commits into from
Closed

fix(riscv): reject compressed double-precision memory ops without D #237

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
55043dd
refactor(riscv): split vector semantics out of cpu.rs
carlosqwqqwq Aug 11, 2026
3e1d1b4
fix(riscv): reject compressed double-precision memory ops without D
carlosqwqqwq Aug 11, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
25 changes: 25 additions & 0 deletions src/isa/riscv/compressed.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,9 @@ fn decode_q0(h: u16, funct3: u32, rv64: bool, isa: &Isa) -> Insn {
}
0b001 => {
// C.FLD -> fld rd', off(rs1') (RV32 & RV64; double)
if !isa.d {
return ill(h);
}
let off = (bits(h, 12, 10) << 3) | (bits(h, 6, 5) << 6);
mk(Op::Fld, rd_, rs1_, 0, off as i64, h)
}
Expand All @@ -144,6 +147,9 @@ fn decode_q0(h: u16, funct3: u32, rv64: bool, isa: &Isa) -> Insn {
}
0b101 => {
// C.FSD -> fsd rs2', off(rs1')
if !isa.d {
return ill(h);
}
let off = (bits(h, 12, 10) << 3) | (bits(h, 6, 5) << 6);
mk(Op::Fsd, 0, rs1_, rvc_reg(bits(h, 4, 2)), off as i64, h)
}
Expand Down Expand Up @@ -348,6 +354,9 @@ fn decode_q2(h: u16, funct3: u32, rv64: bool, isa: &Isa) -> Insn {
}
0b001 => {
// C.FLDSP -> fld rd, off(x2)
if !isa.d {
return ill(h);
}
let off = (bit(h, 12) << 5) | (bits(h, 6, 5) << 3) | (bits(h, 4, 2) << 6);
mk(Op::Fld, rd, 2, 0, off as i64, h)
}
Expand Down Expand Up @@ -420,6 +429,9 @@ fn decode_q2(h: u16, funct3: u32, rv64: bool, isa: &Isa) -> Insn {
return decode_zcmp_zcmt(h, rv64, isa);
}
// C.FSDSP -> fsd rs2, off(x2)
if !isa.d {
return ill(h);
}
let off = (bits(h, 12, 10) << 3) | (bits(h, 9, 7) << 6);
mk(Op::Fsd, 0, 2, bits(h, 6, 2) as u8, off as i64, h)
}
Expand Down Expand Up @@ -608,6 +620,19 @@ mod tests {
);
}

#[test]
fn c_float_mem_rejected_without_d() {
// C.FLD (Q0, funct3=001), C.FLDSP (Q2, funct3=001),
// C.FSD (Q0, funct3=101), C.FSDSP (Q2, funct3=101).
let encodings = [0x2000u16, 0x2002, 0xa000, 0xa002];
let mut no_d = Isa::rv64gc();
no_d.d = false;
for h in encodings {
assert_ne!(decode_rvc(h, Xlen::Rv64, &Isa::rv64gc()).op, Op::Illegal);
assert_eq!(decode_rvc(h, Xlen::Rv64, &no_d).op, Op::Illegal);
}
}

#[test]
fn c_mv_add() {
// c.mv x10, x11 : funct3=100, bit12=0, rd=10, rs2=11
Expand Down
Loading