fix(riscv,x86_64): validate encodings and native replay

[19h]

Overview

This is the next independently implemented rollup following merged #203 and #231. It consolidates the architectural reports in #245, #246, #247, #248, and #249 without taking code or commits from the corresponding contributor branches. It also repairs the host-specific AVX-512 replay failure exposed by the rollup's CI audit on current master.

• reserve masked encodings for all four RVV integer/FP scalar move directions
• validate vrgatherei16.vv index EMUL, alignment, bounds, destination overlap, and mixed-EEW source aliasing
• validate LMUL-sized register groups for the vaadd/vasub vector-vector and vector-scalar families
• enforce all viota.m nonrestartable and operand-overlap constraints before architectural mutation
• reject RV32 OP-IMM shift families when reserved shamt[5]/instruction bit 25 is set, while retaining the RV64 forms
• split the oversized OP-IMM decoder group into a focused module as required by repository size policy
• preserve every architecturally accepted scalar VFIXUPIMM LLIG guest encoding while canonicalizing hosted helper replay to L'L=00, avoiding a processor-specific #UD
• isolate VFIXUPIMM native differential cases so future host signals identify the exact encoding and semantic case

Fixes #245
Fixes #246
Fixes #247
Fixes #248
Fixes #249

Consolidates and supersedes #250, #251, #252, #253, and #254. The RISC-V implementation was derived independently from the issue witnesses and the ISA rules, then validated against QEMU. Carlos is credited as co-author on every rollup commit that incorporates findings originating from these reports.

@carlosqwqqwq, please review the consolidated behavior, expanded sibling coverage, and CI hardening when convenient.

Validation

• cargo fmt --all --check
• cargo clippy --all-targets --features x86_64-suite
• cargo clippy --lib --no-default-features --features x86_64-suite,smir-jit -- -D warnings
• cargo build --all-targets --no-default-features --features x86_64-suite,smir-jit
• exact Linux CI core slice: 8,274 library tests plus every selected integration binary, serial, exit 0
• all 12 focused VFIXUPIMM classifier/lowering/interpreter tests, including the exhaustive 1,720,320-cell classifier partition
• 23 direct RVV validation tests
• direct RV32 decoder coverage for SLLI/SRLI/SRAI/BSETI/BCLRI/BINVI/BEXTI/RORI at bit 25 and legal XLEN controls
• SMIR RV32 decode-frontier rejection coverage
• production JIT fallback coverage at O0 and O2
• RVV opaque SMIR/JIT transactional coverage at O0 and O2
• QEMU RVV differential batch with invalid witnesses and legal controls
• independent qemu-riscv32 probe for 0x02035293: SIGILL/status 132
• CI (including a successful x64 rerun), Cross-build, and Microkernel checks green at 7e14c02c
• dispatched Full Suite green across all 17 jobs at 7e14c02c; its x64 allocation lacked AVX-512, so the native VFIXUPIMM case was feature-skipped while the exhaustive replay encoding tests ran

Change-surface audit

Plane	Result
Direct decode	Affected for RV32 OP-IMM shifts; reserved bit 25 now rejects before dispatch. Scalar VFIXUPIMM guest LLIG acceptance is unchanged.
Direct execute	Affected through centralized pre-execution RVV validation.
CPU state	No layout change; invalid forms trap transactionally before mutation.
Memory/MMU	RISC-V changes are register-only. VFIXUPIMM helper address evaluation and memory-fault ordering are unchanged.
SMIR lift/interpreter	RV32 invalid forms fail at decode; RVV opaque helper shares the validator. VFIXUPIMM canonicalization affects only the hosted replay encoding.
SMIR IR/optimizer	Existing representations are retained and tested at O0/O2.
Native lowering/JIT	Existing RISC-V fallback is retained. Scalar VFIXUPIMM replay now emits canonical ignored L'L bits while preserving every meaningful operand, mask, and immediate control.
Backend/machine/device	Unaffected.
Oracle/C ABI	Unaffected; no public layout or operation taxonomy change.
Tests	Direct, lift, JIT, QEMU differential, exhaustive replay classification, and isolated native-case coverage added.

Assumption Register

ID	Assumption	Basis	Dependent result	Stress test / falsification probe	Status
A1	A successor rollup is required because #203 and #231 cannot accept new commits.	Both PRs are merged on GitHub.	This PR continues their consolidation scope.	gh pr view 203 / gh pr view 231 showing a non-merged state would falsify it.	confirmed
A2	Central RVV validation runs before direct or opaque SMIR/JIT state mutation.	exec_vector calls the validator before dispatch; the helper executes through the same path and copies state only on success.	Transactional rejection without CPU or memory changes.	Reserved-form state snapshots and O0/O2 helper tests would expose a partial commit.	confirmed
A3	Masked scalar-move reservation applies in both read and write directions.	ISA text names vmv.x.s, vmv.s.x, vfmv.f.s, and vfmv.s.f; QEMU agrees.	Expanded #245 coverage beyond its two named witnesses.	Any masked direction executing under QEMU would falsify it.	confirmed
A4	A gather source register cannot be read at both SEW and EEW=16 in one instruction unless those EEWs are equal.	General RVV mixed-EEW source rule; QEMU traps the SEW=8 alias and accepts the SEW=16 control.	Mixed-EEW alias rejection for vrgatherei16.vv.	QEMU differential invalid/control pair.	confirmed
A5	The master/rollup Linux failure is a latent AVX-512 hosted-replay issue rather than a RISC-V regression.	The faulting master bytes are scalar VFIXUPIMMSS; RISC-V-only changes do not reach that path, and non-AVX-512 hosts skip the native case.	In-scope CI hardening on this rollup.	A failure attributable to the changed RISC-V decoder or validator would falsify it.	confirmed
A6	Scalar VFIXUPIMM guest LLIG values remain accepted, but newly emitted hosted replay may canonicalize them.	Intel SDM Vol. 2A says EVEX L'L is generally ignored for scalar instructions; Vol. 2C specifies VFIXUPIMMSS/SD as LLIG. The failing host #UD occurred on replay with L'L=11.	Canonical L'L=00 replay without narrowing guest acceptance.	Exhaustive LLIG classifier tests plus AVX-512-capable Full Suite execution.	confirmed

Out-of-scope findings

None that block this rollup.

[19h]

@carlosqwqqwq, the independently implemented consolidation of #250–#254 is ready for review. Please take a look at the expanded sibling constraints and the direct, SMIR/JIT, and QEMU validation summarized in the description when you have time.

[19h]

CI follow-up: the scheduled Full Suite failure on current master was traced to scalar VFIXUPIMM hosted replay preserving the guest LLIG value L'L=11. The ISA accepts all scalar LLIG values, but that replay encoding #UD'd on the allocated AVX-512 host. Commit 7e14c02 keeps guest acceptance intact and canonicalizes only the emitted helper replay to L'L=00, matching the existing scalar replay policy elsewhere in the JIT. Focused exhaustive tests, formatting, and strict Clippy pass locally; the updated GitHub matrix and Full Suite verification are running.

[19h]

CI update: commit 7e14c02 is green across CI, Cross-build, Microkernel, and the manually dispatched 17-job Full Suite. I also reran the Linux x64 CI job successfully. The available post-fix x64 allocations did not expose AVX-512, so the native VFIXUPIMM differential feature-skipped there; the LLIG guest acceptance and canonical hosted replay bytes are covered by the exhaustive classifier/lowering suite. The PR description now records both the green gates and that hardware-coverage limitation.

[19h]

Follow-up validation and independently reimplemented RISC-V fixes now continue in #296. It consolidates the newly reported vector-memory, operand-validation, SRET, and WFI gaps, carries contributor credit, and is ready for review.