fix(riscv): reject reserved vm=0 encodings of vmv.x.s/vfmv.f.s

[carlosqwqqwq]

fix(riscv): reject reserved vm=0 encodings of vmv.x.s/vfmv.f.s

Closes #245

Summary

The RISC-V V extension reserves the masked (vm=0) encodings of vmv.x.s and vfmv.f.s (RVV 16.2/16.3): these whole-register moves never use the mask register, so the vm bit must be 1. The affected VmvXS / VfmvFS branches executed unconditionally and ignored the vm bit, so reserved encodings such as vmv.x.s a1, v2 with vm=0 were executed and wrote the scalar register. QEMU raises SIGILL for the same encodings.

The fix rejects vm == 0 at the entry of both branches.

Validation

• cargo test --lib: the targeted vmv.x.s/vfmv.f.s tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thank you for reporting #245 and proposing a fix. This is now independently consolidated in #255, which covers the masked encodings for all four integer/FP scalar-move directions and validates the direct, SMIR/JIT, and QEMU paths. To keep review and CI focused on one rollup, I am closing this PR in favor of #255. You are credited as co-author on the rollup commit.