fix(riscv): require aligned index group for vrgatherei16.vv

[carlosqwqqwq]

fix(riscv): require aligned index group for vrgatherei16.vv

Closes #246

Summary

vrgatherei16.vv uses EEW=16 indices with EMUL = ceil(LMUL*16/SEW), and the RISC-V V extension requires every vector register group to be named by its lowest-numbered register (riscv-v-spec, Section 6.3). The affected Vrgather | Vrgatherei16 branch checked destination/source overlap but never validated vs1 % idx_regs == 0, so reserved encodings such as vrgatherei16.vv v16, v8, v1 with e32/m4 (index EMUL=2, vs1=1) were executed. QEMU raises SIGILL for the same encodings.

The fix rejects any vs1 that is not aligned to the index EMUL, for both the vrgatherei16.vv and vrgather.vv forms.

Validation

• cargo test --lib: the targeted vrgatherei16 alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thank you for reporting #246 and proposing a fix. This is now independently consolidated in #255, including exact rational index EMUL, group alignment/bounds, destination overlap, and mixed-EEW source aliasing with direct, SMIR/JIT, and QEMU coverage. To keep review and CI focused on one rollup, I am closing this PR in favor of #255. You are credited as co-author on the rollup commit.