fix(riscv): include enabled H and V bits in the MISA projection - #228
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carlosqwqqwq wants to merge 2 commits into
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fix(riscv): include enabled H and V bits in the MISA projection#228carlosqwqqwq wants to merge 2 commits into
carlosqwqqwq wants to merge 2 commits into
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cpu.rs exceeded the AGENTS.md hard split triggers (2000 lines / 150 kB). Move the vector (RVV) element access and data-path execution group, including set_vtype, into cpu/vector.rs with no behavior change.
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Thank you for reporting and proposing this fix. I independently reimplemented and validated the enabled H/V |
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fix(riscv): include enabled H and V bits in the MISA projection
Closes #227
Summary
The default
rv64gcprofile enables both the H and V extensions, but reading MISA returns a bitmap without bit 7 (H) and bit 21 (V). A guest uses MISA to discover optional architectural extensions, so the returned value is inconsistent with the profile that controls decoding and execution.The fix adds the two enabled single-letter extension bits to the MISA projection. It does not claim that every multi-letter extension must appear in MISA; those are not represented by the single-letter bitmap.
Validation
misa_reports_enabled_h_and_vfails on the base checkout and passes with the fix.cargo test --lib: full library test suite passes with no regressions.No new upstream test files are added; this is a source-only change.