refactor(riscv): split vector semantics out of cpu.rs

[carlosqwqqwq]

Summary

src/isa/riscv/cpu.rs currently exceeds the hard split triggers in AGENTS.md (2000 lines / 150 kB). This change moves the vector (RVV) element access and data-path execution group — sew_bytes through set_vtype, including exec_vector — into a new src/isa/riscv/cpu/vector.rs submodule. No behavior changes: the same methods, in the same order, with exec_vector and set_vtype re-exported as pub(super) for the cpu module.

Validation

• cargo build --locked --release --no-default-features --features smir-jit passes.
• cargo test --lib passes: 8212 passed; 0 failed; 2 ignored.
• Subsequent RVV defect fixes will land on top of this split so they no longer add to the oversized file.

[19h]

Thanks @carlosqwqqwq for doing the module-split work and for keeping the follow-on fixes organized around it. We are consolidating the relevant structure into #203 instead: the rollup centralizes RVV validation in its own module and extracts the touched mixed-width conversion semantics into a focused sibling, alongside the direct/SMIR/JIT/QEMU coverage that depends on those boundaries. We will not take the broader mechanical split as a separate PR, so I am closing #202 as superseded by #203. Your semantic contributions carried into the rollup are credited on the corresponding commits.