fix(riscv): reject vadc/vsbc with vd == v0 - #198
Conversation
|
Review findings:
|
cpu.rs exceeded the AGENTS.md hard split triggers (2000 lines / 150 kB). Move the vector (RVV) element access and data-path execution group, including set_vtype, into cpu/vector.rs with no behavior change.
vadc/vsbc read the carry/borrow-in from v0, so aliasing v0 as the destination is reserved in every implemented form (vv, vxm, vim; vsbc has no immediate form).
faaaeca to
3230355
Compare
|
Thanks for the review. Updated as suggested:
Verified locally: |
|
Thanks @carlosqwqqwq. This fix is being consolidated into rollup PR #203, where it shares centralized direct-interpreter, SMIR/JIT, and QEMU differential coverage with the related RVV corrections. Closing this PR in favor of #203; the relevant rollup commits credit you as co-author. |
fix(riscv): reject vadc/vsbc with vd == v0
Closes #193
Summary
The RISC-V V extension reserves
vadc/vsbcwhen the destination aliasesv0, because the carry/borrow-in is read fromv0in every implemented form.vd == v0now raises an illegal-instruction trap.Validation
vd == v0and legal controls forvadc.vv/vadc.vxm/vadc.vimandvsbc.vv/vsbc.vxm(vsbchas no immediate form).cargo test --lib: cpu suite 72 passed, 0 failed.Notes
The vector semantics moved to
cpu/vector.rsin #202 so this change does not grow the oversizedcpu.rs.