fix(riscv): reject vector FP ops at SEW=8 - #210
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cpu.rs exceeded the AGENTS.md hard split triggers (2000 lines / 150 kB). Move the vector (RVV) element access and data-path execution group, including set_vtype, into cpu/vector.rs with no behavior change.
Vector floating-point operations are only defined for SEW in {16,32,64}; with SEW=8 the encodings are reserved (RVV 1.0). The narrowing FP conversions follow a separate rule (FP-to-int variants are legal at SEW=8), and integer ops at SEW=8 stay legal.
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Thanks @carlosqwqqwq. This fix is being consolidated into rollup PR #203, where it shares centralized direct-interpreter, SMIR/JIT, and QEMU differential coverage with the related RVV corrections. Closing this PR in favor of #203; the relevant rollup commits credit you as co-author. |
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Thanks for consolidating these into #203 and for the co-author credit. The local evidence (QEMU 8.2.2 |
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fix(riscv): reject vector FP ops at SEW=8
Closes #209
Summary
Vector floating-point operations are only defined for SEW in {16,32,64}; with SEW=8 the encodings are reserved and must raise an illegal-instruction exception (RVV 1.0). RAX silently fell back to f64 execution for every vector FP op class at SEW=8. The narrowing FP conversions follow a separate rule (the FP-to-integer variants are legal at SEW=8, tracked separately), and integer ops at SEW=8 stay legal.
Validation
vfadd,vfslide1up.vf,vfwadd), the legal integervaddat SEW=8, and legal SEW (e32) execution of the same FP ops.cargo test --lib: cpu suite 70 passed, 0 failed.Notes
The vector semantics live in
cpu/vector.rsafter the refactor in #202, so this change does not grow the oversizedcpu.rs.