fix(riscv): reject vid.v with non-zero vs2

[carlosqwqqwq]

fix(riscv): reject vid.v with non-zero vs2

Closes #213

Summary

vid.v is a VMUNARY0 instruction whose vs2 field is reserved and must be v0 (RVV §11.14); any other vs2 is a reserved encoding. RAX ignored the field and executed the instruction.

Validation

• Regression covers reserved vs2 values (16 and 3, including the masked form) and the legal vs2 = v0 control.
• cargo test --lib: cpu suite 70 passed, 0 failed.

Notes

The vector semantics live in cpu/vector.rs after the refactor in #202, so this change does not grow the oversized cpu.rs.

[19h]

Thanks @carlosqwqqwq. The reserved nonzero vid.v vs2 fix is now consolidated into #203 in commit 6151a90, with you credited as co-author. The rollup performs the check in centralized pre-execution validation and covers masked/unmasked invalid encodings, legal vs2=v0 controls, transactional SMIR/JIT exits, and live QEMU behavior. Closing this PR in favor of #203.