fix(riscv): reject widening vd/vs2 overlap beyond the high part

[carlosqwqqwq]

fix(riscv): reject widening vd/vs2 overlap beyond the high part

Closes #205

Summary

The widening integer ops (vwadd/vwsub/vwmul/vwmacc families) write a 2*LMUL destination; RVV §5.2 only permits an overlap in the highest-numbered part of the destination group (source group ends where the destination ends). The existing check only covered the OPMVV forms of vwadd/vwsub; the OPMVX forms and the whole widening multiply family bypassed it, so reserved encodings executed normally.

Validation

• Validation extended to funct3=0b010/0b110 and to Vwmulu/Vwmul/Vwmulsu/Vwmaccu/Vwmacc/Vwmaccsu/Vwmaccus; the .w forms use the wide source group width; fractional LMUL keeps one-register source and destination groups.
• CPU regression covers high-part legal overlap, disjoint groups, low-part reserved overlap, misaligned destination, the vx form, and fractional-LMUL cases.
• cargo test --lib: cpu suite 70 passed, 0 failed.

Notes

The vector semantics live in cpu/vector.rs after the refactor in #202, so this change does not grow the oversized cpu.rs.

[19h]

Thanks @carlosqwqqwq. This fix is being consolidated into rollup PR #203, where it shares centralized direct-interpreter, SMIR/JIT, and QEMU differential coverage with the related RVV corrections. Closing this PR in favor of #203; the relevant rollup commits credit you as co-author.

[carlosqwqqwq]

Thanks for consolidating these into #203 and for the co-author credit. The local evidence (QEMU 8.2.2 -cpu max + native RV64 X60, three runs per probe) and the regression tests remain available in this branch if the rollup needs them.