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fix(riscv): require aligned starting register for segment ops - #263

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carlosqwqqwq:fix-riscv-vlseg-vd-align
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fix(riscv): require aligned starting register for segment ops#263
carlosqwqqwq wants to merge 1 commit into
HexRaysSA:masterfrom
carlosqwqqwq:fix-riscv-vlseg-vd-align

fix(riscv): require aligned starting register for segment ops

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build + boot (x86_64 · aarch64 · armv6)
succeeded Aug 13, 2026 in 3m 10s