fix(riscv): require aligned starting register for segment ops

[carlosqwqqwq]

Closes #258

Summary

For vector segment load/store instructions (vlseg* / vsseg*), each field is stored in a register group of EMUL = EEW/SEW * LMUL registers starting at vd, and vd must name the lowest-numbered register of the first field group. The affected Vlseg / Vsseg handler checked only that a field group fits in the register file (emul_regs > 8, nf*emul_regs > 8, vd + nf*emul_regs > 32); it never checked vd % emul_regs == 0, so reserved encodings such as vlseg2e16.v v3, (a0) with EEW=16 and LMUL=1 were executed. QEMU raises SIGILL for the same encodings.

The fix adds the missing vd % emul_regs == 0 check to the segment legality test.

Validation

• cargo test --lib: the targeted segment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated this issue, then reimplemented the accepted behavior with shared direct/SMIR validation and expanded tests in #296. That rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296 so the fixes can be reviewed and merged as one coherent change.