fix(riscv): lift FP and vector with the configured decoder profile - #216
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carlosqwqqwq wants to merge 2 commits into
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fix(riscv): lift FP and vector with the configured decoder profile#216carlosqwqqwq wants to merge 2 commits into
carlosqwqqwq wants to merge 2 commits into
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cpu.rs exceeded the AGENTS.md hard split triggers (2000 lines / 150 kB). Move the vector (RVV) element access and data-path execution group, including set_vtype, into cpu/vector.rs with no behavior change.
The FP and RVV lifters dropped the current RiscVExtensions and decoded with a fixed rv64gc profile, so instructions disabled by the guest profile (e.g. fld with D=0, vadd with V=0) were lifted instead of rejected.
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Thanks @carlosqwqqwq. The configured-profile decoder fix is now consolidated into #203 in commit 4ccda82, with you credited as co-author. The rollup exercises all three FP helper sites with F enabled and D disabled so the regression reaches the hard-coded decoder boundary, plus V-disabled and enabled RVV controls. Closing this PR in favor of #203. |
This was referenced Aug 11, 2026
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fix(riscv): lift FP and vector with the configured decoder profile
Closes #215
Summary
The SMIR FP and RVV lifters dropped the current
RiscVExtensionsand decoded with a fixedrv64gcprofile, so instructions disabled by the guest profile (e.g.fldwith D=0,vadd.vvwith V=0) were lifted instead of rejected. Both paths now use the configured profile decoder.Validation
fldandvadd.vvunder RV64IMAC (must be rejected) and under the full profile (must lift).cargo test --lib: 1 new test passes, full suite unchanged (8213 passed).Notes
This is a translated-path profile gate, distinct from the direct-interpreter CSR gate tracked separately.