mspm0: add OPA driver with buffer and non-inverting PGA modes

embassy-mspm0/Cargo.toml

@@ -70,7 +70,7 @@ critical-section = "1.2.0"
 micromath = "2.0.0"
 
 # mspm0-metapac = { version = "" }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-d9f54366c65cec47957065f42fe04542b852a8cd" }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-cccbd8ec574f5f850067d9058a034959ae6d36be" }
 rand_core = "0.9"
 # Force no cache padding or the types are too large.
 maitake-sync = { version = "0.3.0", default-features = false, features = ["critical-section", "no-cache-pad"]}
@@ -84,7 +84,7 @@ quote = "1.0.40"
 cfg_aliases = "0.2.1"
 
 # mspm0-metapac = { version = "", default-features = false, features = ["metadata"] }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-d9f54366c65cec47957065f42fe04542b852a8cd", default-features = false, features = ["metadata"] }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-cccbd8ec574f5f850067d9058a034959ae6d36be", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]

embassy-mspm0/build.rs

@@ -31,7 +31,11 @@ fn generate_code(cfgs: &mut CfgSet) {
         PathBuf::from(env::var_os("OUT_DIR").unwrap()).display(),
     );
 
-    cfgs.declare_all(&["gpio_pb", "gpio_pc", "int_group1", "unicomm"]);
+    cfgs.declare_all(&["gpio_pb", "gpio_pc", "int_group1", "unicomm", "opa"]);
+
+    if METADATA.peripherals.iter().any(|p| p.kind == "opa") {
+        cfgs.enable("opa");
+    }
 
     let chip_name = match env::vars()
         .map(|(a, _)| a)
@@ -68,6 +72,7 @@ fn generate_code(cfgs: &mut CfgSet) {
     g.extend(generate_interrupts());
     g.extend(generate_peripheral_instances());
     g.extend(generate_pin_trait_impls());
+    g.extend(generate_opa_adc_channels());
     g.extend(generate_groups());
     g.extend(generate_dma_channel_count());
     g.extend(generate_adc_constants(cfgs));
@@ -678,6 +683,7 @@ fn generate_peripheral_instances() -> TokenStream {
             "wwdt" => Some(quote! { impl_wwdt_instance!(#peri); }),
             "adc" => Some(quote! { impl_adc_instance!(#peri); }),
             "mathacl" => Some(quote! { impl_mathacl_instance!(#peri); }),
+            "opa" => Some(quote! { impl_opa_instance!(#peri); }),
             _ => None,
         };
 
@@ -703,6 +709,32 @@ fn generate_peripheral_instances() -> TokenStream {
     }
 }
 
+fn generate_opa_adc_channels() -> TokenStream {
+    // OPA outputs are internally routed to fixed ADC channels. This mapping
+    // is not present in mspm0-data, so it is reproduced here from the TI
+    // SDK's `ADC12_internalConnections.js` (SysConfig metadata).
+    let mapping: &[(&str, &str, u8)] = match METADATA.family {
+        "mspm0g150x" | "mspm0g350x" => &[("OPA0", "ADC0", 13), ("OPA1", "ADC1", 13)],
+        "mspm0l130x" | "mspm0l134x" => &[("OPA0", "ADC0", 12), ("OPA1", "ADC0", 13)],
+        _ => &[],
+    };
+
+    let mut impls = Vec::<TokenStream>::new();
+
+    for (opa, adc, channel) in mapping {
+        let exists = |name| METADATA.peripherals.iter().any(|p| p.name == name);
+        if exists(*opa) && exists(*adc) {
+            let opa = format_ident!("{}", opa);
+            let adc = format_ident!("{}", adc);
+            impls.push(quote! { impl_opa_adc_channel!(#opa, #adc, #channel); });
+        }
+    }
+
+    quote! {
+        #(#impls)*
+    }
+}
+
 fn generate_pin_trait_impls() -> TokenStream {
     let mut impls = Vec::<TokenStream>::new();
 
@@ -729,6 +761,13 @@ fn generate_pin_trait_impls() -> TokenStream {
                 ("tim", "CCP1_CMPL") => Some(quote! { impl_tim_pin!(#peri, #pin_name, #pf, CompCh1); }),
                 ("tim", "CCP2_CMPL") => Some(quote! { impl_tim_pin!(#peri, #pin_name, #pf, CompCh2); }),
                 ("tim", "CCP3_CMPL") => Some(quote! { impl_tim_pin!(#peri, #pin_name, #pf, CompCh3); }),
+                // OPA pin channels are the CFG.PSEL mux values from the
+                // MSPM0 TRM. IN2+ shares the DAC_OUT pad and is selected
+                // through the DAC12 PSEL channel.
+                ("opa", "IN0+") => Some(quote! { impl_opa_non_inverting_pin!(#peri, #pin_name, 1u8); }),
+                ("opa", "IN1+") => Some(quote! { impl_opa_non_inverting_pin!(#peri, #pin_name, 2u8); }),
+                ("opa", "IN2+") => Some(quote! { impl_opa_non_inverting_pin!(#peri, #pin_name, 3u8); }),
+                ("opa", "OUT") => Some(quote! { impl_opa_output_pin!(#peri, #pin_name); }),
                 ("uart", "TX") => Some(quote! { impl_uart_tx_pin!(#peri, #pin_name, #pf); }),
                 ("uart", "RX") => Some(quote! { impl_uart_rx_pin!(#peri, #pin_name, #pf); }),
                 ("uart", "CTS") => Some(quote! { impl_uart_cts_pin!(#peri, #pin_name, #pf); }),

embassy-mspm0/src/adc.rs

@@ -217,7 +217,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> {
         });
     }
 
-    fn setup_blocking_channel(&mut self, channel: &Peri<'d, impl AdcChannel<T>>) {
+    fn setup_blocking_channel(&mut self, channel: &Peri<'_, impl AdcChannel<T>>) {
         channel.setup();
 
         // CTL0.ENC must be 0 to write the MEMCTL register
@@ -262,7 +262,7 @@ impl<'d, T: Instance, M: Mode> Adc<'d, T, M> {
     }
 
     /// Read one ADC channel in blocking mode using the config provided at initialization.
-    pub fn blocking_read(&mut self, channel: &Peri<'d, impl AdcChannel<T>>) -> u16 {
+    pub fn blocking_read(&mut self, channel: &Peri<'_, impl AdcChannel<T>>) -> u16 {
         self.setup_blocking_channel(channel);
         self.enable_conversion();
         self.start_conversion();
@@ -292,7 +292,7 @@ impl<'d, T: Instance> Adc<'d, T, Async> {
         .await;
     }
 
-    fn setup_async_channel(&self, id: usize, channel: &Peri<'d, impl AdcChannel<T>>, vrsel: Vrsel) {
+    fn setup_async_channel(&self, id: usize, channel: &Peri<'_, impl AdcChannel<T>>, vrsel: Vrsel) {
         let vrsel = vals::Vrsel::from_bits(vrsel as u8);
         // Conversion mem config
         self.info.regs.memctl(id).modify(|reg| {
@@ -316,7 +316,7 @@ impl<'d, T: Instance> Adc<'d, T, Async> {
     }
 
     /// Read one ADC channel asynchronously using the config provided at initialization.
-    pub async fn read_channel(&mut self, channel: &Peri<'d, impl AdcChannel<T>>) -> u16 {
+    pub async fn read_channel(&mut self, channel: &Peri<'_, impl AdcChannel<T>>) -> u16 {
         channel.setup();
 
         // CTL0.ENC must be 0 to write the MEMCTL register
@@ -351,12 +351,12 @@ impl<'d, T: Instance> Adc<'d, T, Async> {
     /// adc.read_sequence(sequence.into_iter(), &mut readings).await;
     /// defmt::info!("Measurements: {}", readings);
     /// ```
-    pub async fn read_sequence<'a>(
+    pub async fn read_sequence<'a, 'b: 'a>(
         &mut self,
-        sequence: impl ExactSizeIterator<Item = (&'a Peri<'d, AnyAdcChannel<T>>, Vrsel)>,
+        sequence: impl ExactSizeIterator<Item = (&'a Peri<'b, AnyAdcChannel<T>>, Vrsel)>,
         readings: &mut [u16],
     ) where
-        'd: 'a,
+        T: 'b,
     {
         assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
         assert!(

embassy-mspm0/src/lib.rs

@@ -22,6 +22,8 @@ pub mod i2c;
 pub mod i2c_target;
 #[cfg(any(mspm0g150x, mspm0g151x, mspm0g350x, mspm0g351x))]
 pub mod mathacl;
+#[cfg(opa)]
+pub mod opa;
 pub mod tim;
 #[cfg(any(mspm0g150x, mspm0g151x, mspm0g350x, mspm0g351x, mspm0l122x, mspm0l222x))]
 pub mod trng;