fix(riscv): make sip.SSIP software-writable regardless of mideleg

[carlosqwqqwq]

Summary

The sip CSR's SSIP bit must be software-writable regardless of mideleg; mideleg only controls interrupt delegation, not writability. RAX's Csr::Sip write branch used supervisor_software_interrupt_mask() = mideleg & (1<<1), so with mideleg=0 writing sip.SSIP=1 was silently dropped.

This change uses a fixed SSIP mask (1 << 1) & xmask() for sip writes, decoupling writability from delegation.

Validation

• New regression test sip_ssip_writable_without_mideleg: SSIP set/clear works with mideleg=0, and non-SSIP sip bits are not stored.
• cargo test --lib targeted test passes; full suite shows no regressions.

Closes #308

[carlosqwqqwq]

The test-core (linux-x64) failure is unrelated to this patch: it fails in the x86-64 evex_fma3_* / legacy_sha_replay native-replay tests (SIGILL or SHA assertion), while this PR only touches RISC-V CSR code. The same tests pass locally (full cargo test --lib on master + this patch) and on the linux-arm64/macos lanes.

Root cause: this PR's CI merge base is master, which does not yet contain the scalar EVEX FMA3 LLIG canonicalization from #296 (src/smir/ir/x86_native_replay/classifiers/evex_scalar_fma_llig.rs). Until #296 lands, the native-replay tests are unstable on hosted linux-x64 runners. Once #296 is merged, these lanes should be stable for every PR based on master.