fix(riscv): require aligned register groups for vsmul

[carlosqwqqwq]

Closes #287

Summary

The signed fractional multiply instruction vsmul names vector register groups in vd, vs2 and (for the .vv form) vs1, and the RISC-V V extension requires each group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected Op::Vsmul branch executed the multiply without any register-group alignment check, so reserved encodings such as vsmul.vv v2, v1, v2 with e32/m2 (vs2=v1 misaligned) were executed. QEMU raises SIGILL for these encodings via opivv_check/opivx_check.

The fix rejects any .vv form with a misaligned vd, vs1 or vs2, and any .vx form with a misaligned vd or vs2, computing EMUL from vtype.

Validation

• Source-only change; no cargo build was run in this environment (build policy). A targeted vsmul alignment test is provided separately in the working tree and is expected to pass: misaligned vs2/vd trap, aligned control executes.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated the vsmul operand-alignment gap, then reimplemented it through the shared RVV validator with expanded tests in #296. The rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296.