fix(riscv): require aligned sources and non-overlapping dest for vmseq family

[carlosqwqqwq]

Closes #278

Summary

The comparison instructions vmseq, vmsne, vmsltu, vmslt, vmsleu, vmsle, vmsgtu and vmsgt name vector register groups in the sources but write a single mask register. The RISC-V V extension requires each source group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2) and the destination must not overlap a source group (Section 5.2). The affected Vmseq | Vmsne | Vmsltu | Vmslt | Vmsleu | Vmsle | Vmsgtu | Vmsgt branch executed the comparison without any check, so reserved encodings such as vmseq.vv v2, v3, v4 with e32/m2 (vs2=v3 misaligned) were executed. QEMU raises SIGILL for these encodings via vext_check_mss/vext_check_ms.

The fix rejects any comparison with a misaligned vs2 (and vs1 for the .vv form) or with vd overlapping a source group, computing EMUL from vtype.

Validation

• cargo test --lib: the targeted comparison-family alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently validated the comparison operand constraints and reimplemented the accepted source-alignment and legal mask-destination overlap behavior with source snapshots in #296. The rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296.