fix(riscv): require aligned destination for vid.v

[carlosqwqqwq]

Closes #277

Summary

vid.v writes one SEW-wide element index per element into a destination vector register group whose EMUL equals LMUL, and the RISC-V V extension requires every vector register group to be named by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected Op::Vid branch executed vd[i] = i without any alignment check, so reserved encodings such as vid.v v1 with e8/m2 were executed. QEMU raises SIGILL for these encodings via trans_vid_v / require_align(a->rd, s->lmul).

The fix rejects any vid.v whose destination register number is not aligned to the current LMUL (mapping the vlmul field of vtype to an EMUL of 1/2/4/8).

Validation

• cargo test --lib: the targeted vid.v alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated the vid.v alignment gap, then reimplemented it through the shared RVV validator with direct and SMIR/JIT coverage in #296. The rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296.