fix(riscv): reject vwredsum/vwredsumu vs1 overlapping vs2 group

[carlosqwqqwq]

Closes #276

Summary

The widening integer reductions vwredsumu.vs and vwredsum.vs read a 2*SEW scalar seed from the single register vs1 (EMUL=1) and a SEW vector group from vs2. The RISC-V V extension forbids reading the same vector register with more than one EEW in a single instruction, so a vs1 inside the vs2 group is a reserved encoding. The affected Vwredsumu | Vwredsum branch only checked sew < 64 and executed the reserved encoding, e.g. vwredsumu.vs v4, v0, v0 with e32/m2. QEMU 11.0.50 raises SIGILL for these encodings via reduction_widen_check.

The fix rejects any vwredsumu.vs/vwredsum.vs whose vs1 lies inside the vs2 group [vs2, vs2 + EMUL).

Validation

• cargo test --lib: the targeted vwredsum overlap tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[carlosqwqqwq]

Withdrawing this PR: the proposed overlap check is incorrect. Per RVV spec, the reduction scalar seed vs1 is read with EEW=SEW (same as the vs2 group elements), so a vs1 register inside the vs2 group does not violate the double-EEW rule (vector-common.adoc: a register cannot be read with two different EEWs in one instruction). The maintainer rollup #203 already encodes the correct semantics in vector_validation.rs (widening_reductions_allow_any_scalar_destination_register: scalar sources/destinations are not LMUL groups and may lie within vs2). QEMU 11.0.50's is_overlapped check is a conservative implementation detail, not a spec requirement. Apologies for the noise.