fix(riscv): require aligned register groups for vmul/vdiv/vrem family

[carlosqwqqwq]

Closes #270

Summary

The multiply/divide/remainder instructions vmul, vmulh, vmulhu, vmulhsu, vdivu, vdiv, vremu and vrem name vector register groups in vd, vs2 and (for the .vv form) vs1, and the RISC-V V extension requires each group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected Vmul | Vmulh | Vmulhu | Vmulhsu | Vdivu | Vdiv | Vremu | Vrem branch executed the arithmetic without any register-group alignment check, so reserved encodings such as vmul.vv v2, v1, v2 with e32/m2 (vs2=v1 misaligned) were executed. QEMU raises SIGILL for these encodings via opivv_check/opivx_check.

The fix rejects any .vv form with a misaligned vd, vs1 or vs2, and any .vx form with a misaligned vd or vs2, computing EMUL from vtype.

Validation

• cargo test --lib: the targeted vmul-family alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated this issue, then reimplemented the accepted operand-group alignment checks through the shared validator and expanded tests in #296. That rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296.