fix(riscv): require aligned vd for non-segment vector memory ops

[carlosqwqqwq]

Closes #259

Summary

The unit-stride (vle, vse), strided (vlse, vsse) and indexed (vlxei, vsxei) vector load/store instructions name a data register group whose size is EMUL = EEW/SEW * LMUL registers (LMUL registers for the indexed forms), and the RISC-V V extension requires each group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected exec_vector_memory branches performed the access without any alignment check, so reserved encodings such as vle32.v v3, (x5) with e32/m2 (vd=v3 misaligned) were executed. QEMU raises SIGILL for these encodings via vext_check_load/vext_check_store/vext_check_ld_index/vext_check_st_index.

The fix rejects a misaligned data group vd, computing EMUL from vtype.

Validation

• cargo test --lib: the targeted vector-load/store alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated this issue, then reimplemented the accepted behavior with shared direct/SMIR validation and expanded tests in #296. That rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296 so the fixes can be reviewed and merged as one coherent change.