fix(riscv): gate RV32 compressed single-precision memory ops on F

[carlosqwqqwq]

Closes #256

Summary

The RV32 compressed single-precision load/store encodings c.flw/c.fsw/c.flwsp/c.fswsp belong to the Zcf extension, which is only defined when the F extension is present. Without F, these code points are reserved and must decode as illegal. The affected RV32 compressed decoder emitted Flw/Fsw for these encodings unconditionally, so a guest configured without F executed them instead of taking an illegal-instruction trap. QEMU raises SIGILL for the same encodings.

The fix adds the F-extension gate to the four RV32 decode paths in the compressed decoder, mirroring the existing D-extension gates for the double-precision compressed loads/stores.

Validation

• cargo test --lib: the targeted compressed-load/store tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thanks for the report and patch. I independently reproduced and validated this issue, then reimplemented the accepted behavior with shared direct/SMIR validation and expanded tests in #296. That rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296 so the fixes can be reviewed and merged as one coherent change.