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Xtensa Port v3.13 Updates - #31

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AniruddhaKanhere merged 15 commits into
FreeRTOS:mainfrom
foss-xtensa:xtensa-merge
Jun 18, 2026
Merged

Xtensa Port v3.13 Updates#31
AniruddhaKanhere merged 15 commits into
FreeRTOS:mainfrom
foss-xtensa:xtensa-merge

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@ianstcdns

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Merge Cadence/Xtensa FreeRTOS port up through v3.13

New Features:

  • Add SMP support for multicore Xtensa subsystems (xclib and newlib)
  • Add support for idma-os library

Various bug-fixes, notably:

  • NX bug-fixes for imprecise exception handling
  • Clear LCOUNT on ISR entry, new task creation

Various optional performance improvements, including:

  • FreeRTOS SMP config option "XT_USE_L2RAM" moves data into L2RAM
    for context switching performance improvements. Disabled by default.
  • FreeRTOS SMP config option "XT_USE_DATARAM" moves per-core data into
    dataram for performance improvements. Disabled by default.

Developed and Tested with FreeRTOS-Kernel v11.2.0
Tested with FreeRTOS-Kernel v11.3.0

Signed-off-by: Ian Thompson ianst@cadence.com

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

ianstcdns and others added 15 commits June 15, 2026 10:43
- Update NX init logic to check whether a software interrupt is
  already registered before provisioning it for the scheduler.
- Add new xt_get_interrupt_handler() API to enable above fix.
- Fix exception dispatch assembly code to correctly provide the
  exception stack frame to imprecise exception handlers (NX only).
- Confirm functionality on windowed/call0 configs with and without
  FreeRTOS MPU support.

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Merge pull request #2 from IPG-TIP-Xtensa/dev-xtensa-smp
- Cadence/Xtensa: Add an assertion for SMP init ordering.
- Cadence/Xtensa: Require RJ.5 tools
- Cadence/Xtensa: SMP fixes to enable multicore Palladium
- Cadence/Xtensa: Update coproc handling for SMP
- Cadence/Xtensa: Limit outstanding CacheOps coming from L2
- Cadence/Xtensa: Update release notes for 3.10 release
- Remove DRAM requirement
- Call main() only for core 0
- Replicate/consolidate per-core intr/coproc data
- Separate initial stacks per-core
- Additional fixes and clean-up
- Update release notes for 3.11 release
- FreeRTOS/SMP: CP save bug-fix

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Extra space required for main() to call printf()
  without overflowing when argv[0] has a long path

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Enables xt_smp example to more accurately profile time
  taken in single vs. multicore test.

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Add per-core xclib reentrancy struct instances
- Redefine reentrant pointer to __getreent() function via
  defining __DYNAMIC_REENT__ in xclib
- Improve build infra to properly support overriding
  CFLAGS in nightly tests
- Bump port rev to 3.12

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Clear coproc owner thread when saving callee-saved state
- Fix coproc init/release functions
- Update readme and release notes

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Removes dependency on XTOS locks
- Clarify v3.12 release notes

Signed-off-by: Ian Thompson <ianst@cadence.com>
- xclib is required for 3.12

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Resolve a couple of errors in <xtensa/xtsubsystem.h>
  when compiled with RJ.5 Xtensa toolchain and C++17.
- Will no longer be necessary with RJ.6.

Signed-off-by: Ian Thompson <ianst@cadence.com>
- LCOUNT needs to be cleared during solicited context switch, ISR entry
- Prevents incorrect zero-overhead execution
- Extra conditional logic required for overlay save/restore

Signed-off-by: Ian Thompson <ianst@cadence.com>
Notes for Version 3.13
----------------------
- FreeRTOS SMP support for newlib (experimental).
- FreeRTOS SMP context switching performance improvements.
- FreeRTOS SMP config option "XT_USE_L2RAM" moves data into L2RAM
  for context switching performance improvements.  Disabled by default.
- FreeRTOS SMP config option "XT_USE_DATARAM" moves per-core data into
  dataram for performance improvements.  Disabled by default.
- Based on FreeRTOS-Kernel V11.2.0 release in 3/2025.
- Numerous fixes and improvements.

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Subsystem patch only required for RJ.5 tool-chain;
  do not apply for builds with earlier tools.

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Single-core multithreaded iDMA support
- SMP iDMA support with pinned tasks
- Example test and build infrastructure

Signed-off-by: Ian Thompson <ianst@cadence.com>
- NX configs were reallocating a channel before it was fully cleaned up

Signed-off-by: Ian Thompson <ianst@cadence.com>
- Xtensa port v3.13 tested and working with FreeRTOS-Kernel version 11.3.0.

Signed-off-by: Ian Thompson <ianst@cadence.com>

@AniruddhaKanhere AniruddhaKanhere left a comment

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Thank you for your contribution @ianstcdns.

The changes look good to me!

@AniruddhaKanhere
AniruddhaKanhere enabled auto-merge (squash) June 18, 2026 22:06
@AniruddhaKanhere
AniruddhaKanhere merged commit a5b5d9b into FreeRTOS:main Jun 18, 2026
@ianstcdns

ianstcdns commented Jun 22, 2026 via email

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@ianstcdns

ianstcdns commented Jul 8, 2026 via email

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3 participants