Rollup of 16 pull requests#159437
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- Boolean target modifiers are now mentioned without a trailing `=` in the messages. - Wording improved for unset target modifiers.
…and NVPTX For AVR, AMDGCN, and NVPTX, crates built with different target CPU values are not generally link-compatible. Add a `requires_consistent_cpu` flag to the target spec and enable it for these targets. When the flag is set, treat `-Ctarget-cpu` as a target modifier and require all linked crates to agree on its value. Reject `-Ctarget-cpu=native` before codegen for targets that set `requires_consistent_cpu` to true. Also do not include `native` in the printed `target-cpus` list for such targets. Add tests covering: - which built-in targets set `requires-consistent-cpu` - cross-crate behavior with and without `requires-consistent-cpu` - that an omitted `-Ctarget-cpu` compares equal to an explicitly specified default CPU - rejection and printing behavior for `native` - precedence of repeated `-Ctarget-cpu` flags in metadata comparison and LLVM IR
Signed-off-by: Connor Tsui <connor.tsui20@gmail.com>
…type diverges a mismatch on `-> impl Iterator<Item = Ty>` only pointed at the signature, not at the call in the returned chain where `Item` actually changed. the failed predicate is useless for this, its already rewritten through the impls it was derived from, so the expected assoc types are read from the opaques own bounds and probed against the returned expression. on divergence the existing `point_at_chain` walk kicks in, same as it does for function arguments. handles the chain at the tail expression, behind a `let` binding, and derived through adapters like `flatten`. unrelated failures stay silent since the probe just doesnt resolve there. fixes rust-lang#106993
There is now only a single "module asm", not one before each line.
The assume here is not really relevant to the purpose of the test, and it's position changed in LLVM 23.
Codegen changed in: llvm/llvm-project@66c1b6f
This doesn't optimize as desired since: llvm/llvm-project@21f439f
These now have additional !guid metadata.
See RUST-159073, this test has been flaky with ``` /checkout/obj/build/x86_64-unknown-linux-gnu/test/debuginfo/function-call.gdb/function-call.debugger.script:11: Error in sourced command file: Couldn't write extended state status: Bad address. ``` on linux CI jobs under various environments and hosts/targets. I tried running this under GDB 15.1 locally (WSL, `x86_64-unknown-linux-gnu`) but could not reproduce. CI typically uses GDB 12.1 with Ubuntu 22.04. So gate this test with min GDB 15.1 which prevents it from running in CI to workaround the flakiness but still allow running it locally under GDB >= 15.1. It's *possible* there's a genuine problem here.
On Arm64EC the variadic portion of a c-variadic call must follow the MS x64 ABI: any argument that does not fit in 8 bytes, or whose size is not 1, 2, 4, or 8 bytes, is passed by reference. rustc's `va_arg` implementation already reads such arguments indirectly, but the caller side in `aarch64::compute_abi_info` passed a scalar `i128` by value (it is not an aggregate, so it bypassed `classify_arg`). The callee then dereferenced the inline value as a pointer, causing an access violation (0xC0000005) at runtime. Mark variadic-tail arguments larger than 8 bytes, or whose size is not a power of two, as indirect on Arm64EC so the caller and the `va_arg` reader agree. Fixed arguments are unaffected: a fixed `i128` is still passed by value, matching MSVC and Clang. Add a codegen test verifying that a variadic `i128` is passed as a pointer while a fixed `i128` is passed by value.
Forwards `clone_from` to `DenseBitSet`'s manual implementation. I don't believe this is currently used but I think it doesn't hurt, since it could be a small performance footgun.
We deprecated these awhile ago, and now all the usages are changed.
…orn3 Convert `-Ctarget-cpu` into a target-modifier for AVR, AMDGCN and NVPTX Crates built for AVR, AMDGCN and NVPTX that specify different values for `-Ctarget-cpu` cannot be soundly linked together. This PR attempts to make `rustc` ensure that no crates with disagreeing values for `-Ctarget-cpu` are linked together. This is achieved by converting `-Ctarget-cpu` into a target-modifier depending on `--target`. To do this, the consistency check for `-Ctarget-cpu` considers mismatching values as inconsistent only for targets for which the new flag `requires_consistent_cpu` is set in their target spec. **Why should `-Ctarget-cpu` be a target-modifier for `nvptx`?** <details><summary>PTX is a single-module contract</summary> <p> PTX requires a binary to start with .version (`ptx$$`) then .target (`sm_$$`). If the ptx contains instructions that are not supported by either .version or .target, the binary is ill-formed and will be rejected by ptxas. The concept of features that can be mixed and matched in a binary does not exist for nvptx and is therefore not supported by LLVM. </p> </details> <details><summary>It prevents the production of bitcode that cannot be codegen'd after linking</summary> <p> A target modifier should prevent configurations that are not composable across crates when those crates are linked together. The most prominent example is when enabling a target feature changes the ABI, making cross-crate calls inherently unsound. In the case of nvptx, ABI mismatch is (at least for now) not the core problem motivating target modifiers. NVIDIA’s documented PTX calling convention has [remained stable since ptx20](https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/index.html#function-calling-sequence). However, in the current state it is possible to produce bitcode that cannot be codegen'd after linking, because some operations are only lowerable for sufficiently new SM/PTX levels. In the best case this results in an LLVM error during the final llc step, but this is not something we should rely on for correctness. nvptx has a special compilation pipeline where instead of linking the final PTX object, instead LLVM bitcode is linked. The resulting artifact is then compiled in one invocation. Now consider crate A which is independently compiled into bitcode with the following rustc arguments: ```Rust //@ compile-flags: --target nvptx64-nvidia-cuda -C target-cpu=sm_70 --crate-type=rlib #[cfg(target_feature = "sm_70")] fn foo() { // cannot be lowered to ptx before "sm_70: so currently produces an LLVM error } #[cfg(not(target_feature = "sm_70"))] fn foo() { // can be lowered to ptx before "sm_70" } pub fn bar() { foo() } ``` Crate A is a dependency of crate B. In the *rustc* invocation of crate B 1. crate B is compiled into bitcode, too 2. both bitcode artifacts are bitcode-linked by *llvm-link* 3. the resulting bitcode artifact is compiled by *llc -mcpu=sm_60* This should now ideally create an LLVM error, because the linked bitcode contains code paths that were selected under `sm_70` assumptions but the final NVPTX codegen is targeting `sm_60`, where those operations are not lowerable. An LLVM error here is better than silent miscompilation, but it’s not a promise we should rely on. A real example where this could happen is the lowering of atomic loads and stores with non-relaxed orderings, which is known to depend on the selected SM level. </p> </details> **Why should `-Ctarget-cpu` be a target-modifier for `amdgcn` and `avr`?** - In case of AVR the target-cpu defines the ISA, which is encoded in the ELF header flags, amdgcn also encodes the cpu directly into those flags - To not rely on *lld* which currently prevents it for both by looking at those flags [AVR](https://github.com/llvm/llvm-project/blob/597ffbe09d5f774f861ee55e50022bf84d7f98e2/lld/test/ELF/avr-flags.s) and [amdgcn](https://github.com/llvm/llvm-project/blob/597ffbe09d5f774f861ee55e50022bf84d7f98e2/lld/test/ELF/amdgpu-elf-flags-err.s) Previous discussions about the topic can be found [here](rust-lang#131799 (comment)) and [here](rust-lang#141468). I also created a [Zulip discussion](https://rust-lang.zulipchat.com/#narrow/channel/131828-t-compiler/topic/Making.20-Ctarget-cpu.20a.20target-modifier.20on.20NVPTX/with/566622679). I am unsure if a MCP is needed before proceeding. If you think so please let me know. Creating *target-modifiers* for NVPTX *target-features* is to be done in a follow-up. cc @kjetilkjeka as target maintainer for NVPTX cc @Flakebi as target maintainer for amdgcn cc @Patryk27 as target maintainer for AVR cc @RalfJung you were very involved in the discussions so far Target modifier tracking issue: rust-lang#136966
Update Enzyme to handle LLVM23 Enzyme just gained support for LLVM23, so update it to unblock our LLVM update. r? nikic
…rn-position, r=estebank fix: point at method call chain when a return-position `impl Trait` assoc type diverges a mismatch on `-> impl Iterator<Item = Ty>` only pointed at the signature, not at the call in the returned chain where `Item` actually changed. the failed predicate is useless for this, its already rewritten through the impls it was derived from, so the expected assoc types are read from the opaques own bounds and probed against the returned expression. on divergence the existing `point_at_chain` walk kicks in, same as it does for function arguments. handles the chain at the tail expression, behind a `let` binding and derived through adapters like `flatten`. unrelated failures stay silent since the probe just doesnt resolve there. fixes rust-lang#106993 r? @estebank
…jake Clarify safety requirements for SIMD shl/shr and masked load/store This PR fixes some safety documentation of SIMD functions. These functions are talked in Zulip topic: [Maybe some safety doc need fixs in intrinsics::simd](https://rust-lang.zulipchat.com/#narrow/channel/131828-t-compiler/topic/Maybe.20some.20safety.20doc.20need.20fixs.20in.20intrinsics.3A.3Asimd/with/609693756). Brief explanation: `simd_shl` and `simd_shr` may accept a `rhs` of negative value, but that value will be interpreted as unsigned and thus violate the requirement that `rhs` is less than `<int>::BITS`. So it's better to add a supplement that `rhs` must be in 0..`<int>::BITS`. Also, the `simd_shl` refer that `shifting in sign bits for signed types`, but left shift always shifts in zero bits. And `simd_masked_load` and `simd_masked_store` need to explicitly state that the corresponding `ptr` must be readable/writable as if by `ptr::read/write`, refering to [portable-simd::core_simd::load_select_ptr](https://doc.rust-lang.org/src/core/portable-simd/crates/core_simd/src/vector.rs.html#451) and [portable-simd::core_simd::store_select_ptr](https://doc.rust-lang.org/src/core/portable-simd/crates/core_simd/src/vector.rs.html#710)
…ypes, r=GuillaumeGomez rustdoc: remove old `--emit` types We deprecated these awhile ago, and now all the usages are changed.
Comment about empty run_passes, fixup of rust-lang#158040 r? @RalfJung
…nterface-panic, r=bjorn3 Fix ICE in `write_interface` when the interface file can't be written Fixes rust-lang#143981. `write_interface` opened the `sdylib` interface file with `fs::File::create_buffered(...).unwrap()`, so any failure to create it (like `-o` into a non-existent or unwritable directory) will ICE instead of reporting a normal error. Emit `FailedWritingFile` instead, matching the rlink and dep-graph write paths. Also drop a stray trailing `"` from the `FailedWritingFile` in `diagnostic.rs` and `error.rs`.
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Rollup of 16 pull requests try-job: dist-various-1 try-job: test-various try-job: x86_64-gnu-aux try-job: x86_64-gnu-llvm-21-3 try-job: x86_64-msvc-1 try-job: aarch64-apple try-job: x86_64-mingw-1 try-job: i686-msvc-*
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…uwer Rollup of 16 pull requests Successful merges: - #150732 (Convert `-Ctarget-cpu` into a target-modifier for AVR, AMDGCN and NVPTX ) - #159301 (Update Enzyme to handle LLVM23) - #159365 (fix: point at method call chain when a return-position `impl Trait` assoc type diverges) - #159402 (Clarify safety requirements for SIMD shl/shr and masked load/store) - #159410 (rustdoc: remove old `--emit` types) - #158398 (Comment about empty run_passes, fixup of #158040) - #158843 (Fix ICE in `write_interface` when the interface file can't be written) - #159302 (Implement `Debug` helpers via `Cell`) - #159332 (Honor field-level lint attributes in non_snake_case) - #159386 (add a fallback for `fmuladdf*`) - #159391 (Update tests for LLVM 23) - #159400 (Update books) - #159401 (Gate `tests/debuginfo/function-call.rs` on min GDB 15.1) - #159404 ([aarch64][win] Pass oversized c-variadic args indirectly on Arm64EC) - #159405 (Manually implement Clone for GrowableBitSet) - #159415 (rustdoc: rename the doc parts metadata params)
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💔 Test for d34058c failed: CI. Failed job:
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PR #150732, which is a member of this rollup, was unapproved. |
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💔 Test for 56fda15 failed: CI. Failed job:
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Successful merges:
-Ctarget-cpuinto a target-modifier for AVR, AMDGCN and NVPTX #150732 (Convert-Ctarget-cpuinto a target-modifier for AVR, AMDGCN and NVPTX )impl Traitassoc type diverges #159365 (fix: point at method call chain when a return-positionimpl Traitassoc type diverges)--emittypes #159410 (rustdoc: remove old--emittypes)write_interfacewhen the interface file can't be written #158843 (Fix ICE inwrite_interfacewhen the interface file can't be written)Debughelpers viaCell#159302 (ImplementDebughelpers viaCell)fmuladdf*#159386 (add a fallback forfmuladdf*)tests/debuginfo/function-call.rson min GDB 15.1 #159401 (Gatetests/debuginfo/function-call.rson min GDB 15.1)r? @ghost
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