mspm0: ClkOut driver

embassy-mspm0/build.rs

@@ -334,6 +334,13 @@ fn get_singletons(cfgs: &mut common::CfgSet) -> Vec<Singleton> {
         }
     }
 
+    // TODO: Generate this more generally for other signals (e.g. FCC_IN, HFCLKIN, HFXIN, HFXOUT, etc)
+    // Generate CLK_OUT manually for SYSCTL.
+    singletons.push(Singleton {
+        name: String::from("CLK_OUT"),
+        cfg: None,
+    });
+
     // DMA channels get their own singletons
     for dma_channel in METADATA.dma_channels.iter() {
         singletons.push(Singleton {
@@ -721,6 +728,7 @@ fn generate_pin_trait_impls() -> TokenStream {
                 }
                 ("i2c", "SDA") => Some(quote! { impl_i2c_sda_pin!(#peri, #pin_name, #pf); }),
                 ("i2c", "SCL") => Some(quote! { impl_i2c_scl_pin!(#peri, #pin_name, #pf); }),
+                ("sysctl", "CLK_OUT") => Some(quote! { impl_clk_out_pin!(#pin_name, #pf); }),
                 ("tim", "CCP0") => Some(quote! { impl_tim_pin!(#peri, #pin_name, #pf, Ch0); }),
                 ("tim", "CCP1") => Some(quote! { impl_tim_pin!(#peri, #pin_name, #pf, Ch1); }),
                 ("tim", "CCP2") => Some(quote! { impl_tim_pin!(#peri, #pin_name, #pf, Ch2); }),

embassy-mspm0/src/lib.rs

@@ -22,6 +22,7 @@ pub mod i2c;
 pub mod i2c_target;
 #[cfg(any(mspm0g150x, mspm0g151x, mspm0g350x, mspm0g351x))]
 pub mod mathacl;
+pub mod sysctl;
 pub mod tim;
 #[cfg(any(mspm0g150x, mspm0g151x, mspm0g350x, mspm0g351x, mspm0l122x, mspm0l222x))]
 pub mod trng;

embassy-mspm0/src/sysctl/c1103_1104.rs

@@ -0,0 +1,58 @@
+//! SYSCTL configuration for MSPM0C1103/4 SYSCTL.
+
+use mspm0_metapac::sysctl::vals;
+
+use crate::sysctl::{ClkOutDiv, div_to_pac};
+
+/// Source and configuration for CLK_OUT pin.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ClkOutSource {
+    /// Use SYSOSC as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Sysosc(Option<ClkOutDiv>),
+
+    /// Use ULPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    UlpClk(ClkOutDiv),
+
+    /// Use LFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    LfClk(Option<ClkOutDiv>),
+
+    /// Use MFPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    MfpClk(ClkOutDiv),
+
+    /// Use HFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Hfclk(Option<ClkOutDiv>),
+}
+
+impl ClkOutSource {
+    pub(super) fn convert_div(self) -> (bool, vals::Exclkdivval) {
+        match self {
+            ClkOutSource::Sysosc(div) => div_to_pac(div),
+            ClkOutSource::UlpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::LfClk(div) => div_to_pac(div),
+            ClkOutSource::MfpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::Hfclk(div) => div_to_pac(div),
+        }
+    }
+
+    pub(super) fn convert_src(self) -> vals::Exclksrc {
+        match self {
+            ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC,
+            ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK,
+            ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK,
+            // FIXME: Wrong name from SVD
+            ClkOutSource::MfpClk(_) => vals::Exclksrc::MFCLK,
+            ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK,
+        }
+    }
+}

embassy-mspm0/src/sysctl/c1105_1106.rs

@@ -0,0 +1,58 @@
+//! SYSCTL configuration for MSPM0C1105/6 SYSCTL.
+
+use mspm0_metapac::sysctl::vals;
+
+use crate::sysctl::{ClkOutDiv, div_to_pac};
+
+/// Source and configuration for CLK_OUT pin.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ClkOutSource {
+    /// Use SYSOSC as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Sysosc(Option<ClkOutDiv>),
+
+    /// Use ULPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    UlpClk(ClkOutDiv),
+
+    /// Use LFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    LfClk(Option<ClkOutDiv>),
+
+    /// Use MFPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    MfpClk(ClkOutDiv),
+
+    /// Use HFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Hfclk(Option<ClkOutDiv>),
+}
+
+impl ClkOutSource {
+    pub(super) fn convert_div(self) -> (bool, vals::Exclkdivval) {
+        match self {
+            ClkOutSource::Sysosc(div) => div_to_pac(div),
+            ClkOutSource::UlpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::LfClk(div) => div_to_pac(div),
+            ClkOutSource::MfpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::Hfclk(div) => div_to_pac(div),
+        }
+    }
+
+    pub(super) fn convert_src(self) -> vals::Exclksrc {
+        match self {
+            ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC,
+            ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK,
+            ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK,
+            // FIXME: Wrong name from SVD
+            ClkOutSource::MfpClk(_) => vals::Exclksrc::MFCLK,
+            ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK,
+        }
+    }
+}

embassy-mspm0/src/sysctl/g110x_150x_310x_350x.rs

@@ -0,0 +1,64 @@
+//! SYSCTL configuration for G110x, G150x, G310x and G350x.
+
+use mspm0_metapac::sysctl::vals;
+
+use crate::sysctl::{ClkOutDiv, div_to_pac};
+
+/// Source and configuration for CLK_OUT pin.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ClkOutSource {
+    /// Use SYSOSC as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Sysosc(Option<ClkOutDiv>),
+
+    /// Use ULPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    UlpClk(ClkOutDiv),
+
+    /// Use LFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    LfClk(Option<ClkOutDiv>),
+
+    /// Use MFPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    MfpClk(ClkOutDiv),
+
+    /// Use HFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Hfclk(Option<ClkOutDiv>),
+
+    /// Use SYSPLLCLK1 as the source.
+    ///
+    /// The divider is optional for this clock source.
+    SysPllClk1(Option<ClkOutDiv>),
+}
+
+impl ClkOutSource {
+    pub(super) fn convert_div(self) -> (bool, vals::Exclkdivval) {
+        match self {
+            ClkOutSource::Sysosc(div) => div_to_pac(div),
+            ClkOutSource::UlpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::LfClk(div) => div_to_pac(div),
+            ClkOutSource::MfpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::Hfclk(div) => div_to_pac(div),
+            ClkOutSource::SysPllClk1(div) => div_to_pac(div),
+        }
+    }
+
+    pub(super) fn convert_src(self) -> vals::Exclksrc {
+        match self {
+            ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC,
+            ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK,
+            ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK,
+            ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK,
+            ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK,
+            ClkOutSource::SysPllClk1(_) => vals::Exclksrc::SYSPLLOUT1,
+        }
+    }
+}

embassy-mspm0/src/sysctl/g151x_351x.rs

@@ -0,0 +1,64 @@
+//! SYSCTL configuration for G151x and G351x.
+
+use mspm0_metapac::sysctl::vals;
+
+use crate::sysctl::{ClkOutDiv, div_to_pac};
+
+/// Source and configuration for CLK_OUT pin.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ClkOutSource {
+    /// Use SYSOSC as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Sysosc(Option<ClkOutDiv>),
+
+    /// Use ULPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    UlpClk(ClkOutDiv),
+
+    /// Use LFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    LfClk(Option<ClkOutDiv>),
+
+    /// Use MFPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    MfpClk(ClkOutDiv),
+
+    /// Use HFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Hfclk(Option<ClkOutDiv>),
+
+    /// Use SYSPLLCLK1 as the source.
+    ///
+    /// The divider is optional for this clock source.
+    SysPllClk1(Option<ClkOutDiv>),
+}
+
+impl ClkOutSource {
+    pub(super) fn convert_div(self) -> (bool, vals::Exclkdivval) {
+        match self {
+            ClkOutSource::Sysosc(div) => div_to_pac(div),
+            ClkOutSource::UlpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::LfClk(div) => div_to_pac(div),
+            ClkOutSource::MfpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::Hfclk(div) => div_to_pac(div),
+            ClkOutSource::SysPllClk1(div) => div_to_pac(div),
+        }
+    }
+
+    pub(super) fn convert_src(self) -> vals::Exclksrc {
+        match self {
+            ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC,
+            ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK,
+            ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK,
+            ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK,
+            ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK,
+            ClkOutSource::SysPllClk1(_) => vals::Exclksrc::SYSPLLOUT1,
+        }
+    }
+}

embassy-mspm0/src/sysctl/g511x_518x.rs

@@ -0,0 +1,72 @@
+//! SYSCTL configuration for G518x.
+
+use mspm0_metapac::sysctl::vals;
+
+use crate::sysctl::{ClkOutDiv, div_to_pac};
+
+/// Source and configuration for CLK_OUT pin.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ClkOutSource {
+    /// Use SYSOSC as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Sysosc(Option<ClkOutDiv>),
+
+    /// Use ULPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    UlpClk(ClkOutDiv),
+
+    /// Use LFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    LfClk(Option<ClkOutDiv>),
+
+    /// Use MFPCLK as the source.
+    ///
+    /// The divider is required for this clock source.
+    MfpClk(ClkOutDiv),
+
+    /// Use HFCLK as the source.
+    ///
+    /// The divider is optional for this clock source.
+    Hfclk(Option<ClkOutDiv>),
+
+    /// Use SYSPLLCLK1 as the source.
+    ///
+    /// The divider is optional for this clock source.
+    SysPllClk1(Option<ClkOutDiv>),
+
+    /// Use USBFLL as the source.
+    ///
+    /// The divider is required for this clock source.
+    UsbFll(ClkOutDiv),
+}
+
+impl ClkOutSource {
+    pub(super) fn convert_div(self) -> (bool, vals::Exclkdivval) {
+        match self {
+            ClkOutSource::Sysosc(div) => div_to_pac(div),
+            ClkOutSource::UlpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::LfClk(div) => div_to_pac(div),
+            ClkOutSource::MfpClk(div) => div_to_pac(Some(div)),
+            ClkOutSource::Hfclk(div) => div_to_pac(div),
+            ClkOutSource::SysPllClk1(div) => div_to_pac(div),
+            ClkOutSource::UsbFll(div) => div_to_pac(Some(div)),
+        }
+    }
+
+    pub(super) fn convert_src(self) -> vals::Exclksrc {
+        match self {
+            ClkOutSource::Sysosc(_) => vals::Exclksrc::SYSOSC,
+            ClkOutSource::UlpClk(_) => vals::Exclksrc::ULPCLK,
+            ClkOutSource::LfClk(_) => vals::Exclksrc::LFCLK,
+            ClkOutSource::MfpClk(_) => vals::Exclksrc::MFPCLK,
+            ClkOutSource::Hfclk(_) => vals::Exclksrc::HFCLK,
+            ClkOutSource::SysPllClk1(_) => vals::Exclksrc::SYSPLLOUT1,
+            // FIXME: Update SVD to define _RESERVED_6 as USBFLL
+            ClkOutSource::UsbFll(_) => vals::Exclksrc::_RESERVED_6,
+        }
+    }
+}