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embassy-rp/cyw43-pio: fix input_sync_bypass for pins >= 32 (GPIOBASE offset) #6391

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embassy-rp/cyw43-pio: fix input_sync_bypass for pins >= 32 (GPIOBASE offset) #6391

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3034760
embassy-rp: offset input_sync_bypass mask by GPIOBASE
Jun 20, 2026
fd1b5a9
cyw43-pio: set input_sync_bypass after set_config
Jun 20, 2026
5df5253
Merge branch 'embassy-rs:main' into fix-input-sync-bypass-gpiobase
cedrivard Jun 24, 2026
8a6cd9b
Merge branch 'embassy-rs:main' into fix-input-sync-bypass-gpiobase
cedrivard Jul 2, 2026
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4 changes: 3 additions & 1 deletion cyw43-pio/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -187,7 +187,6 @@ where
let mut pin_io: embassy_rp::pio::Pin<PIO> = common.make_pio_pin(dio);
pin_io.set_pull(Pull::None);
pin_io.set_schmitt(true);
pin_io.set_input_sync_bypass(true);
pin_io.set_drive_strength(Drive::_12mA);
pin_io.set_slew_rate(SlewRate::Fast);

Expand All @@ -210,6 +209,9 @@ where

sm.set_config(&cfg);

// Must be applied after set_config establishes GPIOBASE.
pin_io.set_input_sync_bypass(true);

sm.set_pin_dirs(Direction::Out, &[&pin_clk, &pin_io]);
sm.set_pins(Level::Low, &[&pin_clk, &pin_io]);

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11 changes: 10 additions & 1 deletion embassy-rp/src/pio/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -308,8 +308,17 @@ impl<'l, PIO: Instance> Pin<'l, PIO> {
}

/// Set the pin's input sync bypass.
///
/// `input_sync_bypass` is indexed relative to the PIO's `GPIOBASE`, which is
/// set by [`StateMachine::set_config`]; call this after configuring the state
/// machine so the offset is correct for pins >= 32 on RP235xB.
pub fn set_input_sync_bypass(&mut self, bypass: bool) {
let mask = 1 << self.pin();
#[cfg(feature = "rp2040")]
let offset = 0u8;
#[cfg(feature = "_rp235x")]
let offset = if PIO::PIO.gpiobase().read().gpiobase() { 16 } else { 0 };

let mask = 1u32 << (self.pin() - offset);
if bypass {
PIO::PIO.input_sync_bypass().write_set(|w| *w = mask);
} else {
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