XTF on arm

.gitignore

@@ -4,7 +4,7 @@
 *.pyc
 *.pyo
 *.swp
-/arch/x86/*.lds
+/arch/*/*.lds
 /cscope.*
 /dist/
 /docs/autogenerated/

Makefile

@@ -1,6 +1,5 @@
 MAKEFLAGS += -rR
 ROOT := $(abspath $(CURDIR))
-export ROOT
 
 # $(xtfdir) defaults to $(ROOT) so development and testing can be done
 # straight out of the working tree.
@@ -19,7 +18,16 @@ endif
 
 xtftestdir := $(xtfdir)/tests
 
-export DESTDIR xtfdir xtftestdir
+# Supported architectures
+SUPPORTED_ARCH := x86
+# Default architecture
+ARCH ?= x86
+# Check if specified architecture is supported
+ifeq ($(filter $(ARCH),$(SUPPORTED_ARCH)),)
+$(error Architecture '$(ARCH)' not supported)
+endif
+
+export ROOT DESTDIR ARCH xtfdir xtftestdir
 
 ifeq ($(LLVM),) # GCC toolchain
 CC              := $(CROSS_COMPILE)gcc
@@ -50,9 +58,12 @@ PYTHON             ?= $(PYTHON_INTERPRETER)
 
 export CC LD CPP INSTALL INSTALL_DATA INSTALL_DIR INSTALL_PROGRAM OBJCOPY PYTHON
 
+# By default enable all the tests
+TESTS ?= $(wildcard tests/*)
+
 .PHONY: all
 all:
-	@set -e; for D in $(wildcard tests/*); do \
+	@set -e; for D in $(TESTS); do \
 		[ ! -e $$D/Makefile ] && continue; \
 		$(MAKE) -C $$D build; \
 	done
@@ -61,7 +72,7 @@ all:
 install:
 	@$(INSTALL_DIR) $(DESTDIR)$(xtfdir)
 	$(INSTALL_PROGRAM) xtf-runner $(DESTDIR)$(xtfdir)
-	@set -e; for D in $(wildcard tests/*); do \
+	@set -e; for D in $(TESTS); do \
 		[ ! -e $$D/Makefile ] && continue; \
 		$(MAKE) -C $$D install; \
 	done

arch/arm/arm32/head.S

@@ -0,0 +1,35 @@
+#include <xtf/asm_macros.h>
+
+#define ZIMAGE_MAGIC_NUMBER 0x016f2818
+
+.arm
+
+/*
+ * Common register usage for assembly boot code
+ *
+ * r10 - DTB physical address (boot CPU only)
+ * r9 - Offset between PA and VA ( PA - VA)
+ */
+ENTRY(_start)
+    /* 8 NOPs that make the compressed kernel bootable on legacy ARM systems */
+.rept 8
+    mov     r0, r0
+.endr
+    b       startup
+    /* Magic number used to identify this is an ARM Linux zImage */
+    .word   ZIMAGE_MAGIC_NUMBER
+    /* The address the zImage starts at (0 = relocatable) */
+    .word   0
+    /* The address the zImage ends at */
+    .word   (_end - _start)
+startup:
+    /* Save DTB pointer */
+    mov     r10, r2
+
+    /* Calculate where we are */
+    ldr     r0, =_start              /* r0 := vaddr(_start) */
+    adr     r8, _start               /* r8 := paddr(_start) */
+    sub     r9, r8, r0               /* r9 := phys-offset */
+
+    /* Start an infinite loop */
+1:  b       1b

arch/arm/arm64/cache.S

@@ -0,0 +1,26 @@
+#include <xtf/asm_macros.h>
+
+/*
+ * flush_dcache_range(start, end)
+ * - x0(start) - start address of a region
+ * - x1(end)   - end address of a region
+ * Clobbers: x2, x3, x4
+ */
+ENTRY(flush_dcache_range)
+    /* Do not modify x0 */
+    mov    x4, x0
+    /* Get the minimum D-cache line size */
+    mrs    x3, ctr_el0
+    ubfm   x3, x3, #16, #19
+    mov    x2, #4
+    lsl    x2, x2, x3
+    sub    x3, x2, #1
+    bic    x4, x4, x3
+    /* Clean and invalidate D-cache line */
+1:  dc     civac, x4
+    add    x4, x4, x2
+    cmp    x4, x1
+    b.lo   1b
+    dsb    sy
+    ret
+ENDFUNC(flush_dcache_range)

arch/arm/arm64/head.S

@@ -0,0 +1,90 @@
+#include <arch/page.h>
+#include <xtf/asm_macros.h>
+#include <xen/xen.h>
+
+/* 1 if BE, 0 if LE */
+#define HEAD_FLAG_ENDIANNESS  0
+#define HEAD_FLAG_PAGE_SIZE   ((PAGE_SHIFT - 10) / 2)
+#define HEAD_FLAG_PHYS_BASE   1
+#define HEAD_FLAGS            ((HEAD_FLAG_ENDIANNESS << 0) | \
+                              (HEAD_FLAG_PAGE_SIZE << 1) |   \
+                              (HEAD_FLAG_PHYS_BASE << 3))
+
+/*
+ * Print a string on the debug console
+ *
+ * Clobbers: x0, x1, x2, x3, x16
+ */
+#define PRINT(s)                                    \
+    adr     x2, 98f;                                \
+    mov     x1, #0;                                 \
+97: ldrb    w3, [x2, x1];                           \
+    add     x1, x1, #1;                             \
+    cbnz    w3, 97b;                                \
+    mov     x0, #CONSOLEIO_write;                   \
+    mov     x16, #__HYPERVISOR_console_io;          \
+    hvc     #XEN_HYPERCALL_TAG;                     \
+.pushsection .rodata.str, "aMS", %progbits, 1;      \
+98: .asciz  s;                                      \
+.popsection
+
+.section ".bss.page_aligned"
+.p2align PAGE_SHIFT
+
+.text
+    b       _start                  /* branch to kernel start, magic */
+    .long   0                       /* Executable code */
+    .quad   0x0                     /* Image load offset from start of RAM */
+    .quad   _end - _start           /* Effective Image size */
+    .quad   HEAD_FLAGS              /* Informative flags, little-endian */
+    .quad   0                       /* reserved */
+    .quad   0                       /* reserved */
+    .quad   0                       /* reserved */
+    .byte   0x41                    /* Magic number, "ARM\x64" */
+    .byte   0x52
+    .byte   0x4d
+    .byte   0x64
+    .long   0                       /* reserved */
+
+
+/* Load a physical address of \sym to \xb */
+.macro load_paddr xb, sym
+    ldr \xb, =\sym
+    add \xb, \xb, x21
+.endm
+
+/*
+ * Common register usage for assembly boot code
+ *
+ * x20 - DTB physical address (boot CPU only)
+ * x21 - Offset between PA and VA ( PA - VA)
+ * x30 - lr
+ */
+ENTRY(_start)
+    /* Save DTB pointer */
+    mov     x20, x0
+
+    /* Calculate where we are */
+    ldr     x22, =_start        /* x22 := vaddr(_start) */
+    adr     x21, _start         /* x21 := paddr(_start) */
+    sub     x21, x21, x22       /* x21 := phys-offset */
+
+    PRINT("- XTF booting -\n")
+
+    PRINT("- Zero BSS -\n")
+
+    load_paddr  x0, __start_bss
+    load_paddr  x1, __end_bss
+
+    bl      flush_dcache_range
+1:  str     xzr, [x0], #8
+    cmp     x0, x1
+    b.lo    1b
+
+    /* Load BSS start address again as x0 has been modified in the upper loop */
+    load_paddr  x0, __start_bss
+    bl      flush_dcache_range
+
+    /* Start an infinite loop */
+    PRINT("- Infinite loop -\n")
+2:  b   2b

arch/arm/decode.c

@@ -0,0 +1,25 @@
+/**
+ * @file arch/arm/decode.c
+ *
+ * Helper routines for decoding arm architectural state.
+ */
+#include <xtf/lib.h>
+#include <xtf/libc.h>
+
+bool arch_fmt_pointer(
+    char **str_ptr, char *end, const char **fmt_ptr, const void *arg,
+    int width, int precision, unsigned int flags)
+{
+    UNIMPLEMENTED();
+    return false;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */

arch/arm/include/arch/arm32/regs.h

@@ -0,0 +1,71 @@
+/**
+ * @file arch/arm/include/arch/arm32/regs.h
+ *
+ * arm32 CPU user registers.
+ */
+#ifndef XTF_ARM32_REGS_H
+#define XTF_ARM32_REGS_H
+
+#include <xtf/types.h>
+
+#ifndef __ASSEMBLY__
+struct cpu_regs
+{
+    uint32_t r0;
+    uint32_t r1;
+    uint32_t r2;
+    uint32_t r3;
+    uint32_t r4;
+    uint32_t r5;
+    uint32_t r6;
+    uint32_t r7;
+    uint32_t r8;
+    uint32_t r9;
+    uint32_t r10;
+    union {
+        uint32_t r11;
+        uint32_t fp;
+    };
+    uint32_t r12;
+    uint32_t sp;
+
+    union {
+        uint32_t lr;
+        uint32_t lr_usr;
+    };
+
+    union {
+        uint32_t pc, pc32;
+    };
+
+    uint32_t cpsr;
+    uint32_t hsr;
+
+    uint32_t sp_usr;
+
+    uint32_t sp_irq, lr_irq;
+    uint32_t sp_svc, lr_svc;
+    uint32_t sp_abt, lr_abt;
+    uint32_t sp_und, lr_und;
+
+    uint32_t r8_fiq, r9_fiq, r10_fiq, r11_fiq, r12_fiq;
+    uint32_t sp_fiq, lr_fiq;
+
+    uint32_t spsr_svc, spsr_abt, spsr_und, spsr_irq, spsr_fiq;
+
+    /* The stack should be 8-byte aligned */
+    uint32_t pad1;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* XTF_ARM32_REGS_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */