Skip to content

Fix FIFO queue size #90

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
xarantolus wants to merge 2 commits into
base: main
Choose a base branch
from
Open

Fix FIFO queue size #90

Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
dc139d6
Fix FIFO queue size
xarantolus May 21, 2026
042e8a9
MCU Temp
xarantolus May 21, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions machine/cortex-m/st/stm32l4/interface/spi.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -317,6 +317,13 @@ static int spi_select_device(void *bus, const spi_device_cfg_t *dev_cfg)
LL_SPI_SetClockPolarity(hspi->Instance, polarity);
LL_SPI_SetClockPhase(hspi->Instance, phase);
LL_SPI_SetDataWidth(hspi->Instance, datasize);
/* FRXTH must track the data width, or RXNE fires at the wrong FIFO
* level and >8-bit reads return corrupt data: half-full for >8-bit
* words, quarter-full otherwise. */
LL_SPI_SetRxFIFOThreshold(
hspi->Instance,
dev_cfg->bits_per_word > 8 ? LL_SPI_RX_FIFO_TH_HALF
: LL_SPI_RX_FIFO_TH_QUARTER);
LL_SPI_SetTransferBitOrder(hspi->Instance, bit_order);

__HAL_SPI_ENABLE(hspi);
Expand Down
Loading