cm4: add wolfCrypt FIPS 140-3 support (sim + CM4 hardware validated)

Author: dgarske

config/examples/cm4-fips.config

@@ -0,0 +1,25 @@
+# Raspberry Pi CM4 (BCM2711) with the wolfCrypt FIPS 140-3 module.
+# Point WOLFBOOT_LIB_WOLFSSL at an unpacked FIPS / FIPS-ready wolfSSL tree.
+# Entropy comes from the BCM2711 RNG200 hardware TRNG (hal/cm4.c). See
+# docs/FIPS.md for the in-core hash-seal procedure (done on-target over UART).
+ARCH?=AARCH64
+TARGET?=cm4
+SIGN?=ECC384
+HASH?=SHA384
+FIPS?=1
+WOLFBOOT_LIB_WOLFSSL?=../wolfssl-5.9.2-gplv3-fips-ready
+DEBUG?=1
+DEBUG_UART?=1
+VTOR?=1
+SPMATH?=1
+NO_ARM_ASM?=1
+PKA?=0
+WOLFTPM?=0
+NO_XIP?=1
+NO_QNX?=1
+IMAGE_HEADER_SIZE?=1024
+WOLFBOOT_SECTOR_SIZE=0x400
+WOLFBOOT_NO_PARTITIONS=1
+WOLFBOOT_RAMBOOT_MAX_SIZE=0x20000000
+WOLFBOOT_LOAD_ADDRESS?=0x3080000
+WOLFBOOT_LOAD_DTS_ADDRESS?=0x400000

config/examples/sim-fips.config

@@ -0,0 +1,22 @@
+# wolfBoot simulator build using the wolfCrypt FIPS 140-3 module.
+# Point WOLFBOOT_LIB_WOLFSSL at an unpacked FIPS (or FIPS-ready) wolfSSL tree.
+# Prototype target for the CM4 FIPS integration (see docs/FIPS.md).
+ARCH=sim
+TARGET=sim
+SIGN?=ECC384
+HASH?=SHA384
+FIPS?=1
+WOLFBOOT_LIB_WOLFSSL?=../wolfssl-5.9.2-gplv3-fips-ready
+WOLFBOOT_SMALL_STACK?=0
+SPI_FLASH=0
+DEBUG=1
+
+# sizes should be multiple of system page size
+WOLFBOOT_PARTITION_SIZE=0x40000
+WOLFBOOT_SECTOR_SIZE=0x1000
+WOLFBOOT_PARTITION_BOOT_ADDRESS=0x80000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x100000
+WOLFBOOT_PARTITION_SWAP_ADDRESS=0x180000
+
+# required for keytools
+WOLFBOOT_FIXED_PARTITIONS=1

docs/FIPS.md

@@ -0,0 +1,82 @@
+# wolfBoot with wolfCrypt FIPS 140-3
+
+This page explains how wolfBoot performs its firmware signature verification with the wolfCrypt FIPS 140-3 module, and what a fully CMVP-validated deployment additionally requires. Read it before making any FIPS claim about a wolfBoot deployment.
+
+## Two distinct things: approved algorithms vs. a validated module
+
+FIPS 140-3 has two separate requirements that are easy to conflate:
+
+1. Using FIPS **approved algorithms** for the security-relevant operations (here: image signature verification and hashing).
+2. Performing those operations inside the **CMVP-validated wolfCrypt module** boundary, with the power-on self-test (POST), the in-core integrity check, and status gating (`wolfCrypt_GetStatus_fips`).
+
+A stock wolfBoot build only addresses (1): it compiles individual `wolfcrypt/src/*.c` files selected by `SIGN`/`HASH`, with no POST or in-core integrity check. Building with `FIPS=1` (this page) addresses (2): wolfBoot links the wolfCrypt FIPS module boundary, runs the POST + in-core check at boot, and refuses to boot unless the module is operational.
+
+A production-validated deployment still requires the **licensed, validated** wolfCrypt FIPS bundle at the exact validated revision (not the evaluation "FIPS-ready" drop), the validated module version, and adherence to the module's Security Policy. Contact wolfSSL (facts@wolfssl.com) for the current certificate, validated module version, and integration guidance for a specific target.
+
+## Approved algorithms for image authentication
+
+wolfBoot authenticates images with a public-key signature over a hash of the image. The default wolfBoot signature algorithm, **ED25519, is NOT FIPS approved** and must not be used for a FIPS configuration.
+
+Approved pairs (select in the target `.config`):
+
+- Signature (`SIGN=`): `ECC256` / `ECC384` / `ECC521` (ECDSA P-256/P-384/P-521), or `RSAPSS2048` / `RSAPSS3072` / `RSAPSS4096` (RSA-PSS).
+- Hash (`HASH=`): `SHA256`, `SHA384`. Match or exceed the signature strength (e.g. P-384 with SHA-384).
+- Set `SPMATH=1` (the single-precision math backend the wolfCrypt FIPS module is validated with).
+
+Not approved for signing: `ED25519`, `ED448`. The post-quantum options (`LMS`/`XMSS`/`ML-DSA`) are governed by separate NIST standards and are out of scope here.
+
+## Getting the FIPS source
+
+Obtain a FIPS wolfCrypt source tree. For evaluation, the FIPS-ready bundle can be downloaded from wolfSSL:
+
+```
+https://www.wolfssl.com/wolfssl-5.9.2-gplv3-fips-ready.zip
+```
+
+Production use requires the licensed, validated FIPS bundle. Unpack it and point wolfBoot at it with `WOLFBOOT_LIB_WOLFSSL`.
+
+## Building wolfBoot with FIPS
+
+The `FIPS=1` build option (`options.mk`) rebuilds the wolfcrypt object list as the validated module boundary in link order (`wolfcrypt_first.o` first, `wolfcrypt_last.o` last, with `fips.o`/`fips_test.o` and the boundary crypto between them - the in-core integrity hash on GCC/ELF is enforced by this link order). Point the build at the FIPS tree and select an approved algorithm pair:
+
+```
+cp config/examples/sim-fips.config .config    # or cm4-fips.config
+make FIPS=1 WOLFBOOT_LIB_WOLFSSL=/path/to/wolfssl-5.9.2-gplv3-fips-ready \
+     SIGN=ECC384 HASH=SHA384 SPMATH=1
+```
+
+`-DHAVE_FIPS` is added by the `FIPS=1` block; `settings.h` in the FIPS tree defines the exact version (the FIPS-ready 5.9.2 bundle reports `HAVE_FIPS_VERSION 7`). The `HAVE_FIPS` block in `include/user_settings.h` enables the module's algorithm set, keeps the RNG/DRBG enabled, and wires the entropy seed (below).
+
+## Entropy source (required)
+
+The FIPS DRBG needs a seed. wolfBoot's lean configuration compiles out the OS seed paths, so a seed is provided via `CUSTOM_RAND_GENERATE_SEED` (the `HAVE_FIPS` block in `include/user_settings.h` keeps the RNG enabled by undoing wolfBoot's `WC_NO_RNG`/`WC_NO_HASHDRBG`). The example wiring points it at `wolfBoot_fips_seed()`, implemented per target: `/dev/urandom` on the simulator (`hal/sim.c`) and the BCM2711 RNG200 hardware TRNG on the CM4 (`hal/cm4.c`). Without a working seed, the ECDSA power-on self-test (which performs a sign) fails with `ECDSA_KAT_FIPS_E` because `wc_GenerateSeed()` returns `NOT_COMPILED_IN`.
+
+## Sealing the in-core integrity hash
+
+The module verifies an in-core integrity hash (HMAC-SHA-256 over the module's code and read-only data) at startup. A fresh build ships with a placeholder, so the first run reports a mismatch; capture the runtime hash and seal it:
+
+1. Build and run with a FIPS callback registered (wolfBoot does this in `src/loader.c`). On a mismatch the module reports the runtime hash; wolfBoot prints it (`FIPS in-core hash = ...`, from `wolfCrypt_GetCoreHash_fips()`), and on the CM4 the test app (`test-app/app_cm4.c`) prints it over UART.
+2. Copy the reported 64-hex-character hash into `verifyCore[]` in `wolfcrypt/src/fips_test.c`.
+3. Rebuild and re-run. `wolfCrypt_GetStatus_fips()` now returns 0 (operational).
+
+The seal is **specific to the exact binary layout**: any code change that shifts the FIPS module's link addresses changes the in-core hash and requires a re-seal. Re-sealing `verifyCore[]` itself does not shift addresses (same-size rewrite), so once the rest of the build is fixed the seal converges in one pass.
+
+## Bare-metal targets
+
+The FIPS module targets a hosted environment; a few things must be provided on bare-metal (the CM4 does all of these):
+
+- **POST entry.** The module registers its POST via a C constructor (`.init_array`), which a hosted runtime runs before `main()`. wolfBoot's bare-metal startup does not run `.init_array`, so build with `NO_ATTRIBUTE_CONSTRUCTOR` and call `fipsEntry()` explicitly (`src/loader.c`).
+- **Normal (cacheable) memory.** wolfBoot's simple startup runs with the MMU off, where all memory is Device-nGnRnE and unaligned / 128-bit SIMD accesses fault (the FIPS module and newlib `printf`/`snprintf` do both). The CM4 HAL enables a minimal identity MMU with DDR mapped Normal cacheable before the POST (`cm4_mmu_enable`), and tears it down (clean D-cache, disable MMU/caches) before the boot handoff (`cm4_mmu_disable`) so the loaded image is coherent and the application starts MMU-off.
+- **libc.** The module uses malloc/printf; provide a heap (`src/store_sbrk.c` + a linker `end` symbol) and stub the remaining newlib syscalls (`--specs=nosys.specs`).
+
+Bring the module up on the simulator (`config/examples/sim-fips.config`) first - it exercises the whole flow (module boundary, POST, in-core seal, verify, A/B update) with no hardware.
+
+## Verifying operation
+
+- POST/CASTs run at module initialization; `wc_RunAllCast_fips()` runs the conditional algorithm self-tests and `wolfCrypt_GetStatus_fips()` reports the module status (0 = operational).
+- wolfBoot treats a non-zero FIPS status as a hard failure and refuses to boot (`src/loader.c`).
+- A deliberately corrupted module boundary (flip a byte) makes the in-core check fail and blocks the boot - the negative test for the integration.
+
+## See also
+
+- [Targets.md](Targets.md) - Raspberry Pi Compute Module 4 (BCM2711) target. FIPS 140-3 authenticated boot (module operational -> SHA-384 integrity -> ECDSA-P384 verify seeded by the BCM2711 hardware TRNG -> handoff) is validated on CM4 hardware.

docs/README.md

@@ -11,6 +11,7 @@ See also: [wolfBoot Product Overview](https://www.wolfssl.com/products/wolfboot/
 - [**encrypted_partitions.md**](./encrypted_partitions.md) - Creating and managing encrypted firmware/data partitions.
 - [**firmware_image.md**](./firmware_image.md) - wolfBoot firmware image format, layout, and metadata.
 - [**firmware_update.md**](./firmware_update.md) - Update flow: slots, verification, rollback, and recovery.
+- [**FIPS.md**](./FIPS.md) - Building wolfBoot with the wolfCrypt FIPS 140-3 module: approved algorithms, DRBG entropy, and in-core integrity sealing.
 - [**flash-OTP.md**](./flash-OTP.md) - Using One-Time Programmable (OTP) regions in flash for secure data.
 - [**flash_partitions.md**](./flash_partitions.md) - Flash partitioning schemes and configuration guidance.
 - [**HAL.md**](./HAL.md) - Hardware Abstraction Layer notes and porting considerations.

docs/Targets.md

@@ -3767,7 +3767,7 @@ Booting at 0x3080000
 
 ### FIPS 140-3
 
-The CM4 target uses `SIGN=ECC384 HASH=SHA384` (FIPS-approved) and can perform its signature verification with the wolfCrypt FIPS 140-3 validated module. The on-target harness in `test-app/app_cm4.c` registers a FIPS callback and prints the runtime in-core integrity hash over the UART for the `verifyCore[]` bootstrap. See [FIPS.md](FIPS.md) for the full build and hash-sealing procedure.
+The CM4 target uses `SIGN=ECC384 HASH=SHA384` (FIPS-approved) and can perform its signature verification with the wolfCrypt FIPS 140-3 module (`config/examples/cm4-fips.config`, `FIPS=1`). At boot the module runs its power-on self-test and in-core integrity check, and wolfBoot refuses to boot unless the module is operational. Entropy for the FIPS DRBG comes from the BCM2711 RNG200 hardware TRNG. This has been validated end to end on CM4 hardware: FIPS module operational -> SHA-384 integrity -> ECDSA-P384 signature verification -> boot handoff. The on-target harness in `test-app/app_cm4.c` prints the runtime in-core hash over the UART for the `verifyCore[]` seal. See [FIPS.md](FIPS.md) for the full build, entropy, and hash-sealing procedure.
 
 ## Xilinx Zynq UltraScale
 

hal/cm4.c

@@ -42,6 +42,11 @@
 /* Fixed addresses (provided by the linker script) */
 extern void *kernel_addr, *update_addr, *dts_addr;
 
+#if defined(HAVE_FIPS)
+void cm4_mmu_enable(void);  /* defined below; called from hal_init */
+void cm4_mmu_disable(void); /* defined below; called from hal_prepare_boot */
+#endif
+
 #if defined(DEBUG_UART)
 static void uart_tx(char c)
 {
@@ -129,12 +134,135 @@ void hal_init(void)
     wolfBoot_printf("wolfBoot CM4 (BCM2711 Cortex-A72) hal_init, EL%d\n",
         (int)((el >> 2) & 0x3));
 #endif
+#if defined(HAVE_FIPS)
+    /* Bring up Normal cacheable memory before the FIPS POST, which uses
+     * unaligned / SIMD accesses that the MMU-off Device memory rejects. */
+    cm4_mmu_enable();
+#endif
 }
 
 void hal_prepare_boot(void)
 {
+#if defined(HAVE_FIPS)
+    /* Undo cm4_mmu_enable() before handoff: flush the app out of the D-cache
+     * and return to the MMU-off state the application expects. */
+    cm4_mmu_disable();
+#endif
 }
 
+#if defined(HAVE_FIPS)
+/* Minimal identity-mapped MMU + caches for the CM4. wolfBoot's simple startup
+ * runs with the MMU off, so all memory is Device-nGnRnE, which faults on the
+ * unaligned / 128-bit SIMD accesses the FIPS module and newlib printf perform.
+ * Mapping DDR as Normal (cacheable) permits those accesses and speeds up the
+ * crypto; the peripheral region (incl. 0xFE000000) stays Device.
+ * Four 1GB block descriptors cover the 32-bit VA space at translation level 1. */
+#define MMU_BLOCK_NORMAL  0x0000000000000701ULL /* block, AttrIdx0, AF, SH inner */
+#define MMU_BLOCK_DEVICE  0x0000000000000405ULL /* block, AttrIdx1, AF, SH none  */
+
+static volatile uint64_t cm4_l1_table[512] __attribute__((aligned(4096)));
+
+void cm4_mmu_enable(void)
+{
+    unsigned long sctlr;
+    int i;
+
+    /* 0-3GB DDR -> Normal; 3-4GB peripherals (0xFE000000) -> Device. */
+    for (i = 0; i < 4; i++) {
+        uint64_t base = (uint64_t)i << 30;
+        cm4_l1_table[i] = base | ((i == 3) ? MMU_BLOCK_DEVICE : MMU_BLOCK_NORMAL);
+    }
+    /* MAIR: Attr0 = 0xFF Normal WB write-alloc, Attr1 = 0x00 Device-nGnRnE. */
+    __asm__ volatile("msr mair_el2, %0" :: "r"(0x00000000000000FFUL));
+    __asm__ volatile("msr ttbr0_el2, %0"
+        :: "r"((uint64_t)(uintptr_t)cm4_l1_table));
+    /* TCR_EL2: T0SZ=32 (32-bit VA), 4KB granule, WB cacheable inner-shareable
+     * table walks, 36-bit PA. */
+    __asm__ volatile("msr tcr_el2, %0" :: "r"(0x0000000000013520UL));
+    __asm__ volatile("isb");
+    __asm__ volatile("tlbi alle2");
+    __asm__ volatile("dsb sy");
+    __asm__ volatile("ic iallu");
+    __asm__ volatile("dsb sy");
+    __asm__ volatile("isb");
+    /* SCTLR_EL2: enable MMU (M), data cache (C), instruction cache (I). */
+    __asm__ volatile("mrs %0, sctlr_el2" : "=r"(sctlr));
+    sctlr |= (1UL << 0) | (1UL << 2) | (1UL << 12);
+    __asm__ volatile("msr sctlr_el2, %0" :: "r"(sctlr));
+    __asm__ volatile("isb");
+}
+
+/* Clean+invalidate all data cache levels by set/way (dc cisw). */
+static void cm4_dcache_flush_all(void)
+{
+    uint64_t clidr, ccsidr;
+    unsigned int level, loc, ctype, linesize, ways, sets, way, set, wayshift;
+
+    __asm__ volatile("dsb sy");
+    __asm__ volatile("mrs %0, clidr_el1" : "=r"(clidr));
+    loc = (unsigned int)((clidr >> 24) & 0x7); /* Level of Coherency */
+    for (level = 0; level < loc; level++) {
+        ctype = (unsigned int)((clidr >> (level * 3)) & 0x7);
+        if (ctype < 2) /* no data/unified cache at this level */
+            continue;
+        __asm__ volatile("msr csselr_el1, %0" :: "r"((uint64_t)(level << 1)));
+        __asm__ volatile("isb");
+        __asm__ volatile("mrs %0, ccsidr_el1" : "=r"(ccsidr));
+        linesize = (unsigned int)(ccsidr & 0x7) + 4;          /* log2(bytes) */
+        ways     = (unsigned int)((ccsidr >> 3) & 0x3FF);     /* assoc - 1 */
+        sets     = (unsigned int)((ccsidr >> 13) & 0x7FFF);   /* sets - 1 */
+        wayshift = (unsigned int)__builtin_clz(ways);
+        for (set = 0; set <= sets; set++) {
+            for (way = 0; way <= ways; way++) {
+                uint64_t val = ((uint64_t)(level << 1))
+                    | ((uint64_t)way << wayshift)
+                    | ((uint64_t)set << linesize);
+                __asm__ volatile("dc cisw, %0" :: "r"(val));
+            }
+        }
+    }
+    __asm__ volatile("dsb sy");
+    __asm__ volatile("isb");
+}
+
+/* Tear down the MMU/caches before boot handoff: clean the freshly-copied app
+ * out of the D-cache to memory, disable the MMU and caches, and invalidate the
+ * I-cache/TLB. Returns the CPU to the MMU-off state the application (and the
+ * ARM64 Linux boot protocol) expects. */
+void cm4_mmu_disable(void)
+{
+    unsigned long sctlr;
+
+    cm4_dcache_flush_all();
+    __asm__ volatile("mrs %0, sctlr_el2" : "=r"(sctlr));
+    sctlr &= ~((1UL << 0) | (1UL << 2) | (1UL << 12)); /* clear M, C, I */
+    __asm__ volatile("msr sctlr_el2, %0" :: "r"(sctlr));
+    __asm__ volatile("isb");
+    __asm__ volatile("ic iallu");
+    __asm__ volatile("tlbi alle2");
+    __asm__ volatile("dsb sy");
+    __asm__ volatile("isb");
+}
+#endif /* HAVE_FIPS */
+
+#if defined(DEBUG) && defined(DEBUG_UART)
+/* CM4 bring-up diagnostic: exception handler invoked from cm4_vectors in
+ * src/boot_aarch64_start.S. Dumps the fault syndrome so a data/instruction
+ * abort shows up over UART instead of hanging silently. Built only with
+ * DEBUG + DEBUG_UART. ESR_EL2[31:26] = exception class. */
+void cm4_fault_handler(unsigned long esr, unsigned long elr, unsigned long far);
+void cm4_fault_handler(unsigned long esr, unsigned long elr, unsigned long far)
+{
+    wolfBoot_printf("\n*** CM4 EXCEPTION ***\n");
+    wolfBoot_printf("ESR_EL2=0x%08x EC=0x%02x\n",
+        (unsigned)esr, (unsigned)((esr >> 26) & 0x3F));
+    wolfBoot_printf("ELR_EL2=0x%08x%08x\n",
+        (unsigned)(elr >> 32), (unsigned)elr);
+    wolfBoot_printf("FAR_EL2=0x%08x%08x\n",
+        (unsigned)(far >> 32), (unsigned)far);
+}
+#endif /* DEBUG && DEBUG_UART */
+
 #if defined(HAVE_FIPS)
 /* FIPS DRBG entropy seed from the BCM2711 RNG200 hardware TRNG. Registered via
  * CUSTOM_RAND_GENERATE_SEED in include/user_settings.h. The RNG200 has NIST
@@ -176,18 +304,6 @@ int wolfBoot_fips_seed(unsigned char* output, unsigned int sz)
         for (i = 0; i < n; i++)
             output[pos++] = (unsigned char)(word >> (i * 8));
     }
-
-#if defined(DEBUG_UART)
-    {
-        static int traced = 0;
-        if (!traced) {
-            wolfBoot_printf("RNG200 seed %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                output[0], output[1], output[2], output[3],
-                output[4], output[5], output[6], output[7]);
-            traced = 1;
-        }
-    }
-#endif
     return 0;
 }
 #endif /* HAVE_FIPS */

hal/sim.c

@@ -122,6 +122,28 @@ static int sim_cryptocb(int devIdArg, wc_CryptoInfo* info, void* ctx)
 #include "port/posix/posix_flash_file.h"
 #endif /* WOLFBOOT_ENABLE_WOLFHSM_SERVER */
 
+#if defined(HAVE_FIPS)
+/* FIPS DRBG entropy seed for the simulator: read from /dev/urandom.
+ * Registered via CUSTOM_RAND_GENERATE_SEED in include/user_settings.h. */
+int wolfBoot_fips_seed(unsigned char* output, unsigned int sz)
+{
+    unsigned int pos = 0;
+    int fd = open("/dev/urandom", O_RDONLY);
+    if (fd < 0)
+        return -1;
+    while (pos < sz) {
+        ssize_t r = read(fd, output + pos, sz - pos);
+        if (r <= 0) {
+            close(fd);
+            return -1;
+        }
+        pos += (unsigned int)r;
+    }
+    close(fd);
+    return 0;
+}
+#endif /* HAVE_FIPS */
+
 /* Global pointer to the internal and external flash base */
 uint8_t *sim_ram_base;
 static uint8_t *flash_base;